Evaluating the Impact of Increasing System Fault Currents on

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Evaluating the Impact of Increasing System Fault Currents on

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Evaluating the Impact of Increasing System Fault Currents on Protection
Zhihan Xu, Ilia Voloh – GE Grid Solutions, LLC Mohsen Khanbeigi – Hydro One
Abstract — Every year the capacity of power systems is increasing, meaning that short circuit current levels are continuously going up. The ratings of instrument transformers at many existing substations that were designed many years ago are now becoming underrated with present fault current levels. Such a situation is obviously concerning to protection engineers who strive to ensure security and dependability of the protection is not jeopardized. Besides risks of trivial CT saturation, which affects the security of the protection system, the concern is if a particular relay is capable of processing such high current, while maintaining adequate accuracy to ensure protection security and dependability.
This paper first reviews the causes of increasing short circuit current level in power systems. Some historic and present fault current levels are described. Then, the impacts of increasing short current on protective relays are investigated in detail, in terms of signal processing algorithms, relay clamping level and CT saturation. A thought analysis is presented to examine the security and dependability of a specified transformer differential protection system. Some evaluation techniques and methods are introduced for the purpose of generalized analysis.
Index Terms — Increasing Short Circuit Current, Transformer Differential Relay, CT Saturation
I. INTRODUCTION When a short circuit occurs on a power system, several things happen [1]:
 At the short circuit location, arcing and burning can occur.  Short circuit current flows from the various sources to the short circuit location.  All components carrying the short circuit currents are subject to thermal and mechanical
stress.  System voltage drops in proportion to the magnitude of the short circuit current.
The level of short circuit current is directly related to the size and capacity of the power sources and is independent of the load current of the circuit protected by the protective device. The larger the capacity of the power sources, the greater the short circuit current will be.
Basically, there are five power sources contributing to the short circuit current:  Generators  Synchronous Motors  Induction Motors  Electric Utility Systems  Distribution Generations
Nowadays, the short circuit levels in power systems are continuously increasing compared to their historical levels.

A. Causes of increasing fault current in power systems The major reasons that cause the incrementing of fault current are summarized as below:
 Installation of new transmission facilities, transformers and generation Due to the growth of power demand, more and more new transmission lines, transformers and generators are being installed in the power system. Equivalently in the circuit model, the Thevenin equivalent impedance seen at system buses is being reduced by these conditions. Consequently, the fault current level is increasing, simply according to the Ohm’s law.
 Additions and changes to existing generators The upgrading of existing generators will increase the capacity of power sources, and therefore result in the larger fault currents.
 Reconfigurations of the bulk electric system (BES) network The short circuit, system stability, steady state power flow, and other types of analyses are required to be re-evaluated for reconfigurations or restructuring of the electrical generation resources, transmission lines, interconnections with neighboring systems, such as changes in interconnection location or increasing voltage level of a substation. These changes could result in larger fault currents.
 New distribution generation The renewable energy resources, such as solar, wind, biomass, geothermal etc. are growing fast and getting more stakes in the utility's energy portfolio. By the end of 2014, the total renewable power capacity exceeded 309 GW in North America, and 1,828 GW worldwide [2]. The connection of such distribution generations to the conventional power grids will increase the fault current levels since the total fault levels are now contributed by the combination of the upstream grid and the distribution generation.
The detailed short circuit current calculation methods can be found in the IEC standard 60909-0 [3], including the calculation of the contribution of wind power station units and power station units with full size converters to the short-circuit current. And some examples are also described in the IEC technical report 60865-2 [4]. More conveniently, the short circuit analysis programs, such as ETAP and ASPEN, can be used to model the specific power system and determine short circuit currents.
B. Historic and present fault levels The Transmission System Code (TSC) published by the Ontario Energy Board (OEB) sets out the minimum standards that an electricity transmitter must meet in designing, constructing, managing and operating its transmission system [5]. The present and some historic values of the maximum allowable fault levels set out by the OEB are listed in Table 1. The values in the table do not mean that the power system would truly experience such fault current levels.
The maximum fault currents in some of main substations in the Hydro One network are summarized in Table 2. The requirements of circuit breaker interrupting capacity in the Hydro One are given in Table 3. It is estimated that the short circuit current level has increased by 27% in the Hydro One system in the last twenty years.

Table 1. Maximum allowable fault levels set out by OEB

Nominal Voltage (kV) 500 230 115 44 27.6 (4-wire) 27.6 (3-wire) 13.8

Maximum 3-Phase Fault (kA) 80 (usually limited to 63 kA) 63 50 20 17 17 21

Maximum SLG fault (kA) 80 (usually limited to 63 kA) 80 (usually limited to 63 kA) 50 19 (usually limited to 8 kA) 12 0.45 10

Table 2. Maximum fault levels in Hydro One network (2015)

Nominal Voltage (kV) 500 230 115

Fault Current (up to kA) 50.47 73 32.69

Table 3. Circuit breaker interrupting capacity requirement

Nominal Voltage (kV) 500 230 115

1990s (kA) 40/63 40/50/63 40/50

Present (kA) 63/80 50/63/80 40/50/63

C. Questions raised from protection engineers The increased fault current causes the electrical devices to experience more thermal and mechanical stress. The protective relays are supposed to correctly operate to interrupt the fault current flowing through the protected equipment. However, relay misoperation, slow operation and failure to operate may be expected as the relay performance may be jeopardized in such scenarios.
Moreover, it can be predicted that the short circuit current level will further increase in the future. Considering the effects of the increasing fault current level on protective relays, protection engineers would ask the following questions:
 What will be the impact of increasing fault current on protection relays?  Will relays be reliable or not under such situations?  What are effects on the dependability and security of a relay?  How to evaluate a specific system and relay under such circumstances?  How to upgrade relay or adjust relay settings to increase dependability and security?
These questions will be discussed in the following sections, the examples will be analyzed, and the solutions will be provided and explained.

II. IMPACT OF INCREASING FAULT CURRENT ON PROTECTIVE RELAYS
A. Signal processing algorithms The phasor and true root mean square (rms) value are the two most used quantities in relays. Normally, the true rms is calculated as the square root of the arithmetic mean of the squares of a set of raw samples in one cycle. The calculated rms value can truly represent the primary current regardless of the current level, if:
 the secondary current is not distorted by current transformer (CT) saturation or CT measurement error.
 the errors caused by analog-to-digital converter (ADC) quantization error, fixed point operations in relays, and anti-aliasing filter can be neglected.

The phasor estimation is used to calculate the fundamental magnitude and angle of the input signal. Two commonly used estimation techniques are Discrete Fourier Transform (DFT) and Cosine filter. Normally, a filtering technique is applied to remove DC decaying transients, which is prior to the phasor estimation by DFT. The above two techniques can be considered as a linear process such that the output is proportional to the input and the increased fault current level has no effect on the phasor estimation algorithms.

B. ADC range and clamping
Due to the conversion range of ADC, different relays normally have different clamping levels such that digital current samples will be clamped if they exceed levels. A simple example is shown below, where the clamping level is 10 pu and the current peak value is two times the clamping level.

Current (pu)

Clamp level = 10 pu

20

Ideal Current

Clamped Current 15

10

5

0

-5

-10

-15

-20

0

0.005

0.01

0.015

0.02

0.025

0.03

Time (s)

Figure 1. Example of clamped current

The digital samples clamped by ADC will not precisely express the secondary analog current, and they induce erroneous measurements and harmonics. The fundamental magnitude and rms values

of the clamped values are illustrated in Figure 2. Apparently, the lower clamp level results in the smaller magnitude and rms value. For example, if the clamp level is 50% of the peak value, the magnitude of the clamped current is 60.9% of ideal value, and rms is reduced to 62.5%. One more example, assuming that the clamp level is 28pu and the symmetrical fault current is 39.6pu (56pu for peak value), then the calculated magnitude will be 24.1pu, rather than the expected 39.6pu. It should be noted that the phase angle shift in the clamped currents is negligible.

Ratio of magnitude & RMS to ideal mag

1

Ratio of Mag to Ideal

0.9

Ratio of RMS to Ideal

0.8

0.7

X: 49.99

Y: 0.6255

0.6

X: 49.99

0.5

Y: 0.6091

0.4

0.3

0.2

0.1

0 0 10 20 30 40 50 60 70 80 90 100
Ratio of clamp level to peak (%)
Figure 2. Magnitude and rms of clamped currents

Ratio of harmonics to fundamental mag (%)

The clamped currents induce the odd harmonics, but no even harmonics. The ratios of harmonics to the fundamental magnitude are shown in Figure 3. It should be mentioned that the fundamental magnitude here is calculated from the clamped current instead of the ideal current.
35 Third Harmonic Fifth Harmonic
30 Seventh Harmonic Ninth Harmonic
25
20
15
10
5
0 0 10 20 30 40 50 60 70 80 90 100
Ratio of clamp level to peak (%)
Figure 3. Ratio of harmonics to fundamental of clamped currents

It can be concluded that:
 The clamp level will reduce the current magnitude and rms values, which affects protection functions that are related to the current magnitude or rms values.
 The current phasor angle is not affected by the clamping mechanism.  There is no erroneous even harmonics resulted from the clamping mechanism.  However, erroneous odd harmonics are induced. For a constant clamp level and third
harmonic, the larger fault current will result in the larger ratio of odd harmonics to fundamental magnitude if the current samples exceed the clamp level. Particularly, the ratio of the fifth harmonic to fundamental may be used to inhibit the transformer differential function during overexcitation conditions. Therefore, if the overexcitation inhibit mode is enabled, the transformer differential function may fail to operate on a severe fault due to the presence of the incorrect fifth harmonic induced by clamping. An instantaneous (unbiased/ unrestrained) differential function with a well-considered pickup setting is helpful to avoid such situation and increases the relay dependability.
C. CT saturation Basically, there are five factors which contribute to CT saturation [6]:
 High primary fault current  Low accuracy voltage class (due to improper CT selection/sizing)  Excessive secondary burden  Heavy DC offset in current  Large percent remanence
The increase in primary fault current will increase secondary current, sequentially, increase exciting voltage, enter into the saturated region and significantly increase exciting current. As a result, the secondary current is greatly reduced and distorted.
When the CTs are selected with lower than required accuracy voltages or the low CT ratios are selected, the CT can go into saturation for the fault currents due to lower knee point voltage of the CT characteristics.
Larger CT burdens increase exciting voltage under the same fault current, and increase exciting current. Then CT is more likely to saturate.
The maximum DC component of a fault occurs when the instantaneous voltage is zero. Then the DC component starts decaying according to the time constant of the primary power system. The larger time constant will result in the longer decaying process, and then longer CT saturation period.
Remanence is the magnetic flux that is retained in the magnetic circuit after the removal of the excitation. Remanence may remain in either positive or negative direction. When the CT is subject to subsequent fault current again, the flux changes will start from the remanent value. Then the shifted remanence may worsen the transient response by pushing the core into deeper

saturation within a shorter time if the remanence and instantaneous flux have the same direction, or improve the transient response by keeping the core away from the deeper saturation if the remanence and instantaneous flux have the opposite direction.
The first factor (high primary fault current) in the above five factors will be discussed in this section. Due to the increased fault current, the existing CT may start saturating or experience the heavier saturation.
The CT secondary excitation characteristics curve is a practical way to represent the CT steadystate performance. This curve is normally provided by manufacturers and can be easily verified during field tests. The excitation curve maps the relationship between the root-mean-square (rms) value of the secondary exciting voltage and the rms value of the secondary exciting current. The Figure 4 shows an 800/5A CT excitation characteristic obtained during a field test.
103

Exciting Voltage (V, rms)

102

101

CT Ratio: 800/5A

100 10-4

Secondary resistance: 0.281 ohm
10-3 10-2 10-1 100 101
Exciting Current (A, rms)

Figure 4. An 800/5A CT secondary excitation characteristics

In order to analyze the transient behavior of current transformers, this paper utilizes a simplified CT model proposed by the IEEE Power System Relaying Committee (PSRC) [7].

The AC saturation is caused by the symmetrical current with no DC component. A set of AC saturation examples is shown in Figure 5, which is generated by the PSRC model.

In order to avoid ac saturation [8], the secondary saturation voltage, VX, must satisfy the following

equation.

VX  IS  ZS

(1)

where, IS is the primary current divided by the turns ratio, and ZS is the total secondary burden (RS + XS + ZB). It can be observed that the AC saturation may be caused by the higher primary current, lower ratio CT (such as ground CT), or a larger CT burden (long lead length, and/or small

AWG wire gage). Therefore, the AC saturation can be avoided by properly increasing the CT saturation voltage, CT ratio, or decreasing CT burden.

1.5

CT Ratio: 800:5

Burden: 2.1 ohms

1

Ratio Current

[email protected]: 700V

DC offset: 0%

0.5

Current (pu of fault)

0

-0.5 Saturated Secondary Current (40-80 kA)
-1

-1.5

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Time (s)

Figure 5. Examples of AC saturation

The DC saturation is commonly caused by the DC component in the fault current, unipolar half wave current or remnant flux in the CT. Once the transients decay enough or vanish so that the saturated region is not entered, the CT would get back to the steady state. A set of DC saturation examples caused by the fully DC offset is shown in Figure 6.

Current (pu of fault)

2.5 Ratio Current
2
1.5

CT Ratio: 800:5 Burden: 2.1 ohms [email protected]: 700V DC offset: 100% X/R: 17

1

0.5

0

-0.5

Saturated Secondary -1 Current (20-80 kA)

0.02

0.03

0.04

0.05

0.06

0.07

0.08

Time (s)

Figure 6. Examples of DC saturation

To avoid DC saturation (but ignoring effect of remanence), the required saturation voltage is given below,
VX  IS  ZS  (1 X ) (2) R
where X/R is the primary system X/R ratio. Comparing Eq. (1) with Eq. (2), it can be found that the knee point voltage to avoid DC saturation must be (1+X/R) times that required for avoiding AC saturation.
Taking AC saturation currents in Figure 5 as an example, the magnitude, rms, angle shift, and ratio of harmonics to fundamental are shown below.

RMS (pu of fault)

Magnitude (pu of fault)

40 kA

60 kA

1

80 kA

Ideal

0.8

0.6

40 kA

60 kA

1

80 kA

Ideal

0.8

0.6

Angle shift (degree)

0.4

0.4

0.2

0.2

Ratio of harmonics to fundamental (%)

0

0

0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

Time (s)

Time (s)

45

110

40 kA

40

60 kA

80 kA

35

80 kA, 2nd Harmonic

100

80 kA, 3rd Harmonic

90

80 kA, 4th Harmonic

80 kA, 5th Harmonic

80

30 70

25

60

20

50

40 15
30
10 20

5

10

0

0

0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

Time (s)

Time (s)

Figure 7. Magnitude, rms, angle shift and ratio of harmonics to fundamental (AC saturation)

It can be observed that:
 As expected, the deeper saturation will result in lower magnitude and rms value than the ideal values.
 The rms value is slightly higher than the corresponding magnitude since the waveform is distorted.

 The saturation will result in the leading angle. The deeper the saturation, the larger the leading angle will be.
 Taking the 80 kA fault current as an example, the ratios of even harmonics to fundamental will decay to zero less than 1.5 cycles after fault inception, but the ratios of odd harmonics to fundamental will reduce to a non-zero constant level. It should be noted that this decaying duration of 1.5 cycles is different from the decaying processing of the ratio of 2nd harmonic to fundamental in the transformer differential function, which takes quite longer time as described in Section IV-B.

Similarly, the relative analysis results of DC saturation currents in Figure 6 are shown below. The DC removal technique has been applied below to remove the DC decaying components in DC saturation waveforms.

Magnitude (pu of fault)

1.6

20 kA

1.4

50 kA

1

80 kA

1.2 Ideal

0.8 1

RMS (pu of fault)

0.6

0.8

Ratio of harmonics to fundamental (%)

0.4

0.2

0

0.02

0.04

0.06

0.08

0.1

Time (s)

100

90

80

70

60

50

40

30

20

10

20 kA 50 kA 80 kA Ideal

0.12

0.14

20 kA 50 kA 80 kA

0.6

0.4

0.2

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Time (s)

110

80 kA, 2nd Harmonic

100

80 kA, 3rd Harmonic

90

80 kA, 4th Harmonic

80 kA, 5th Harmonic

80

70

60

50

40

30

20

10

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Time (s)

Time (s)

Figure 8. Magnitude, rms, angle shift and ratio of harmonics to fundamental (DC saturation)

Angle shift (degree)

It can be observed that:
 The deeper saturation will result in lower magnitude and rms value than the ideal values and take longer time to get stable.
FaultLevelMagnitudeHarmonicsCircuit