Lecture 6 Leakage and Low-Power Design
Transcript Of Lecture 6 Leakage and Low-Power Design
Lecture 6
Leakage and Low-Power Design
R. Saleh Dept. of ECE University of British Columbia [email protected]
RAS
Lecture 6
1
Methods of Reducing Leakage Power
• So far we have discussed dynamic power reduction techniques which result from switching-related currents
• The transistor also exhibits many current leakage mechanisms that cause power dissipation when it is not switching
• In this lecture, we will explore the different types of leakage currents and their trends
• We will then describe ways to limit various types of leakage • We will also re-examine the DSM transistor in more detail as a
side-effect of this study • Readings:
– Sections of Chapter 2 and 3 in HJS – Many books and papers on DSM leakage power – Alvin Loke Presentation (SSCS Technical Seminar, 2007)
RAS
Lecture 6
2
Basic CMOS Transistor Structure
• Typical process today uses twin-tub CMOS technology • Shallow-trench isolation, thin-oxide, lightly-doped drain/source • Salicided drain/source/gate to reduce resistance • extensive channel engineering for VT-adjust, punchthrough
prevention, etc. • Need to examine some details to understand leakage
n+
n+
p+
p+
STI
p-well
STI
n-well
STI
common substrate
RAS
Lecture 6
3
Sources of Leakages
Ȋ Leakage is a big problem in the recent CMOS technology nodes Ȋ A variety of leakage mechanisms exist in the DSM transistor Ȋ Acutal leakage levels vary depending on biasing and physical
parameters at the technology node (doping, tox, VT, W, L, etc.)
I1: Subthreshold Current I2: DIBL I2’: Punchthrough I3: Thin Oxide Gate Tunneling I4: GIDL I5: PN Junction Current I6: Hot Carrier Injection
RAS
Lecture 6
4
Relative Importance of Leakage Currents
But is this really true? Need to examine each one and their trends…
RAS
Lecture 6
5
Hot carriers
• Assume gate and drain are connected to VDD • Carriers pick up high energy from electric field as they move across
channel – become “hot” carriers which are attracted to gate node
– These “hot” carriers may be injected into the gate oxide where they
become trapped – cause a shift in the VT
VDD
Use lightly-doped drain
to reduce hot-electrons
Gnd
VDD
n+
n+
– Accumulation of charge in oxide causes shift in VT over time • The higher the VDD, the hotter the carriers (more current) • Since we have scaled VDD, the problem was under control for years
• However, the VDD value may not scale in the future so this problem may again be an issue
RAS
Lecture 6
6
Source/Drain Leakage
• Source and drain junctions are normally reverse-biased so they will leak current
• Typically very small but may increase with scaling since doping levels are very high in future technologies (breakdown voltage decreases as doping increases – use LDD to reduce BV)
g sd
nMOS
n+
n+
p
n+ to p substrate substrate must be p
Look at cross-section
pMOS
p+
p+
n
substrate must be n
IS/D (uA/um)
1 1E-2 1E-4 1E-6 1E-8
10nm
100nm
1000nm
RAS
Lecture 6
7
Thin-Oxide Gate Tunneling
• tox has been scaling with each technology generation
• We have reached the point where tox is so small the direct
tunneling occurs (tox < 2nm) o
• Gate leakage = f(tox, VG)
90nm 1V-CMOS 20A gate oxide
VDD
Gnd
n+
VDD
n+
p
• NMOS leakage is 3-10X PMOS leakage (electrons vs. holes)
o
o
• Below 20 A, the leakage increases by 10X for every 2A in gate
thickness reduction
RAS
Lecture 6
8
High-k Metal Gate
Traditional Oxide
HK+MG (45nm)
45nm 65nm 90nm 130nm
High-k Metal Gate
Low resistance layer
Metal Gate
High-k oxide
S
D
RAS
Lecture 6
9
Subthreshold Leakage
• Subthreshold leakage is the most important contributor to static power
in CMOS
q (VGS −VT −Voffset )
− qVDS
Isub = Is ⋅ e nKT (1 − e KT )
Pstatic ≈ IsubVDD
• Note that it is primarily a function of VT • Higher VT, exponentially less current!
Isub
−VT
Isub ∝ Io ⋅ enKT / q
VT
• But gate overdrive (VGS-VT) is also a linear function of VT
• Need to understand VT in more detail to find ways to reduce leakage
RAS
Lecture 6
10
Leakage and Low-Power Design
R. Saleh Dept. of ECE University of British Columbia [email protected]
RAS
Lecture 6
1
Methods of Reducing Leakage Power
• So far we have discussed dynamic power reduction techniques which result from switching-related currents
• The transistor also exhibits many current leakage mechanisms that cause power dissipation when it is not switching
• In this lecture, we will explore the different types of leakage currents and their trends
• We will then describe ways to limit various types of leakage • We will also re-examine the DSM transistor in more detail as a
side-effect of this study • Readings:
– Sections of Chapter 2 and 3 in HJS – Many books and papers on DSM leakage power – Alvin Loke Presentation (SSCS Technical Seminar, 2007)
RAS
Lecture 6
2
Basic CMOS Transistor Structure
• Typical process today uses twin-tub CMOS technology • Shallow-trench isolation, thin-oxide, lightly-doped drain/source • Salicided drain/source/gate to reduce resistance • extensive channel engineering for VT-adjust, punchthrough
prevention, etc. • Need to examine some details to understand leakage
n+
n+
p+
p+
STI
p-well
STI
n-well
STI
common substrate
RAS
Lecture 6
3
Sources of Leakages
Ȋ Leakage is a big problem in the recent CMOS technology nodes Ȋ A variety of leakage mechanisms exist in the DSM transistor Ȋ Acutal leakage levels vary depending on biasing and physical
parameters at the technology node (doping, tox, VT, W, L, etc.)
I1: Subthreshold Current I2: DIBL I2’: Punchthrough I3: Thin Oxide Gate Tunneling I4: GIDL I5: PN Junction Current I6: Hot Carrier Injection
RAS
Lecture 6
4
Relative Importance of Leakage Currents
But is this really true? Need to examine each one and their trends…
RAS
Lecture 6
5
Hot carriers
• Assume gate and drain are connected to VDD • Carriers pick up high energy from electric field as they move across
channel – become “hot” carriers which are attracted to gate node
– These “hot” carriers may be injected into the gate oxide where they
become trapped – cause a shift in the VT
VDD
Use lightly-doped drain
to reduce hot-electrons
Gnd
VDD
n+
n+
– Accumulation of charge in oxide causes shift in VT over time • The higher the VDD, the hotter the carriers (more current) • Since we have scaled VDD, the problem was under control for years
• However, the VDD value may not scale in the future so this problem may again be an issue
RAS
Lecture 6
6
Source/Drain Leakage
• Source and drain junctions are normally reverse-biased so they will leak current
• Typically very small but may increase with scaling since doping levels are very high in future technologies (breakdown voltage decreases as doping increases – use LDD to reduce BV)
g sd
nMOS
n+
n+
p
n+ to p substrate substrate must be p
Look at cross-section
pMOS
p+
p+
n
substrate must be n
IS/D (uA/um)
1 1E-2 1E-4 1E-6 1E-8
10nm
100nm
1000nm
RAS
Lecture 6
7
Thin-Oxide Gate Tunneling
• tox has been scaling with each technology generation
• We have reached the point where tox is so small the direct
tunneling occurs (tox < 2nm) o
• Gate leakage = f(tox, VG)
90nm 1V-CMOS 20A gate oxide
VDD
Gnd
n+
VDD
n+
p
• NMOS leakage is 3-10X PMOS leakage (electrons vs. holes)
o
o
• Below 20 A, the leakage increases by 10X for every 2A in gate
thickness reduction
RAS
Lecture 6
8
High-k Metal Gate
Traditional Oxide
HK+MG (45nm)
45nm 65nm 90nm 130nm
High-k Metal Gate
Low resistance layer
Metal Gate
High-k oxide
S
D
RAS
Lecture 6
9
Subthreshold Leakage
• Subthreshold leakage is the most important contributor to static power
in CMOS
q (VGS −VT −Voffset )
− qVDS
Isub = Is ⋅ e nKT (1 − e KT )
Pstatic ≈ IsubVDD
• Note that it is primarily a function of VT • Higher VT, exponentially less current!
Isub
−VT
Isub ∝ Io ⋅ enKT / q
VT
• But gate overdrive (VGS-VT) is also a linear function of VT
• Need to understand VT in more detail to find ways to reduce leakage
RAS
Lecture 6
10