# Low-power dual-element memristor based memory design

## Transcript Of Low-power dual-element memristor based memory design

Low-power Dual-element Memristor Based Memory Design

Dimin Niu†, Yiran Chen‡, Yuan Xie†

†Pennsylvania State University, University Park, PA ‡Seagate Technology, Bloomington, MN, USA †{dun118, [email protected]} ‡[email protected]

ABSTRACT

Recently, the emerging memristor device technology has attracted signiﬁcant research interests due to its distinctive hysteresis characteristic, which potentially can enable novel circuit designs for future VLSI circuits. In particular, characteristics such as non-volatility, non-linearity, low power consumption, and good scalability make memristor one of the most promising emerging memory technologies. Some important design parameter, however, such as speed, energy consumption, and distingushiablility, are mainly determined by the memristor’s physical characteristics. In this paper, a key observation of memristor’s asymmetric energy consumption is made by the detailed analysis of the transient power consumption. Based on this observation, we propose a dualelement memory structure in which each memory cell consists of two memristors. By constantly writing complement bits into the two elements within a cell, the dual-element is ﬂexible to satisfy design constraints which are usually diﬃcult to be satisﬁed with one-cell memory structure. Design space of the dual-element memory cell is studied and it shows that the trade-oﬀs among the energy, speed, and distingushiablility should be explored for diﬀerent design objectives. In particular, we show that under the energy-driven optimization, the proposed dual-element memory achieves the same programming speed and distinguishability as conventional single-element memory but the energy consumption can be reduced by up to 80%.

Categories and Subject Descriptors

B.7.1 [INTEGRATED CIRCUITS]: Types and Design Styles—Memory technologies

General Terms

Design, Measurement

Keywords

Memristor, Low Power, Nonvolatile Memory

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1. INTRODUCTION

Memristor, known as the fourth basic circuit element, was ﬁrst theoretically predicted by Chua in 1971 [1], and practically demonstrated by HP Labs in 2008 [2]. This emerging technology has many attractive features, including non-volatility, non-linearity, low-power, and good scalability. Such properties grant memristor the potential for innovations for future circuit and system architecture designs. For example, as memristor can accomplish most of the behaviors of the synapse such as remembering the past dynamic history and storing a continuous set of states, it has the potential to realize electronic neural networks [3] [4]. Some practical approaches of analog circuits with memristor have been proposed based on its non-linearity property [5] [6] [7]. In addition, non-volatility and good scalability make memristor a promising candidate as the next-generation highdensity, high-performance memory technology [8], and it has been predicted that memristor-based memory will be a strong competitor against other emerging memory technologies such as phase-change memory (PCRAM) and SpinTorque-Transfer Magnetic memory (STT-RAM) [8] [9].

For memory design, reducing the energy consumption is one of the most important design metrics for both high-end computing applications or low-end embedded applications. In this paper, we perform a comprehensive study to analyze the power and energy consumption of memristor-based memory design which adopts HP’s thin-ﬁlm memristor technology [2]. Based on the observations from our analysis, we propose a novel dual-element memristor based memory structure. In this novel structure, each memory cell contains two memristors, within which the complement bits are stored. During the read operation, the diﬀerential signals will be read out, and converted to logic ‘0’ or ‘1’. By writing complement bits into the two elements within a cell, the dual-element is ﬂexible to satisfy design constraints which usually cannot be achieved by one-cell memory structure. Design space of the dual-element is studied in this paper and it shows that a trade-oﬀ among the energy, speed, and distingushiablility should be explored for optimization of different objectives.

2. PRELIMINARIES

2.1 Memristor Model

The memristor is formally deﬁned as a two-terminal element in which the magnetic ﬂux between the terminals is a function of the amount of electric charge q that can pass through the device, which is explicitly expressed by the

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Figure 1: Structure and model of memristor cell

equation dϕ = M dq, where M is called the memristance. If the relation is linear, memristance becomes constant and the memristor acts as a resistor. By contract, if it is non-linear, the memristance varies with the charge, which determines the hysteretic behavior of current/voltage proﬁle, and can be deﬁned as M (q). Generally, a memristive system can be described by the following relations:

V (t) = M (ω, i, t)I(t)

ω = f (ω, i, t) ,

(1)

where ω is the variable that indicates the internal state of the memristive system, V (t) and I(t) denote the voltage and current across the memristive system. Note, M is the memristance and depends on the system state, current, as well as time. If the memristance in Equation (1) only depends on the cumulative eﬀect of current, it becomes a charge dependent device, and is called a current-controlled memristor.

The structure of HP’s memristor cell is shown in Fig. 1(a) [2]. In this metal-oxide-metal structure, the top electrode and the bottom electrode are two thick metal wires on Pt, and two titanium dioxide ﬁlms are sandwiched by the electrodes. The upper titanium oxide is doped with oxygen vacancies, noted as T iO2−X , and has relatively high conductivity as a semiconductor. The lower oxide, which is perfect titanium oxide without dopants, has its natural state as an insulator. When a biased voltage is applied cross the thin ﬁlm, the oxygen vacancies are driven from the doped oxide to the undoped oxide and consequently lower the memristance of the whole cell. Contrarily, with a reversed bias voltage, the dopants migrate back to the doped oxide.

Based on the dopant drifting characteristics, the memristor can be modeled as a two-terminal device, which is made up of three resistors in series. Fig 1(b) shows the schematic of memristor model. The thicknesses of the upper and bottom oxides are Ltop and Lbtm, respectively. The upper oxide has a constant resistance of Rtop. But the resistance of the bottom oxide depends on the status of the oxide. We can denote the full undoped resistance as Roff and the full doped resistance as Ron. Obviously, Rtop, Ron, and Roff has the relationship as: Roff Ron, Roff Rtop, and Rtop/Ron = Ltop/Lbtm.

Since Rtop is a constant and relatively small, the total resistance is predominantly determined by the status of the bottom oxide. The state variable ω is deﬁned as the proportion of the length of the doped region to the total length of the bottom oxide, as shown in Fig. 1(b). Thus, the mathematical model for the memristance of the cell can be described by the resistances and the internal state ω as [2]:

M (ω) = Rtop + ωRon + (1 − ω)Roff ,

(2)

Under a biased voltage v(t), the length of the doping region

will change, which results in the change of the state variable ω. For example, a positive voltage causes the dopants (oxygen vacancies) to drift to the undoped region and therefore result in a lower memristance of the whole memristor. In the linear drift model, the boundary between the doped and undoped region drifts at a constant speed as: vdrift = µvRoni(t)/Lbtm. Based on this fact, the memristor can be modeled as [2]:

v(t) = (Rtop + ωRon + (1 − ω)Roff ) · i(t)

dω = µv ρTiO2−x i(t)

(3)

dt

LS

and the internal state (ω) can be deduced as:

ω(t) = ξ1 − (α0 − ξ1 )2 − λ ϕ(t) ,

(4)

ξ2

ξ2

ξ2

where ξ1 = Roff +Rtop, ξ2 = Roff −Ron, and λ = 2µvρ/LS. Also, α0 denotes the initial state of the memristor. Since the parameters ξ1, ξ2 and λ are constants and only depend on the material and manufacture process, the internal state ω can be considered as a ﬂux-driven variable. Accordingly, the memristance is determined by the ﬂux applied to it, regardless the waveform of the input voltage. Considering the ﬂux is the integral of voltage on time, if a square wave pulse is applied to the cell, the change of the memristance consequently depends on the pulse width of the input voltage. In this case, these properties make it suitable to employ memristor as a voltage-driven memory cell.

2.2 Memristor-based Memory

Attractive properties of the memristor such as non-volatility, high distinguishability, low-power, scalability and fast accessing speed make it a promising candidate for the nextgeneration high-density and high performance memory technology [8][10]. Consequently, memristor-based memory structure has been studied recently [8]. The basic structure of memristor-based memory is very similar to a typical memory array such as SRAM-based and DRAM-based memory, which consist of the word line decoder, memory array, sense ampliﬁer and output MUX. However, due to the special electronic characteristics of memristor, several additional peripheral circuits, such as pulse generator and R/W selector, should be added to implement the write/read operations. With the non-volatility and the ﬂux-driven properties, the key features for the memristor-based memory can be summarized as follows:

1) Information Storage: It has been reported that the oﬀ-to-on resistance ratios of HP’s memristor can achieve as much as 1000 [11], which implies a good distinguishability of the memristor-based memory. Since the memristance can reﬂect the internal state ω of the memristor, we can deﬁne the high resistance as logic ‘0’ and the low resistance as logic ‘1’. In addition, in the presence of noise, a safety margin should be deﬁned to ensure the reliability of the cell.

2) Write Operation: The write operation is to change the internal state of the memristor and therefore change the information stored in the cell. A simple way to write the memristor is to apply enough positive (writing logic ‘1’) or negative (writing logic ‘0’) voltage to the memristor cell. By applying a square wave pulse to the cell, the net ﬂux is only determined by the polarity and pulse width of the input

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voltage. Thus, one can carefully adjust the input voltage to ensure the correct write operation.

3) Read Operation: The read operation is more complicated than the write. To read a memristor cell, a voltage is applied across the cell and the current is converted to voltage output by a sense ampliﬁer. Besides, in order to avoid the disturbing read and ensure the stabilization of the memristor’s internal state, a two-state read operation is proposed in [8]. The read pattern contains a negative pulse and a positive pulse with the same magnitude and duration, makeing sure zero net ﬂux is imported into the memristor cell.

4) Refresh Scheme: If the waveform of the read operation is not perfectly symmetrical, the net ﬂux applied to the memristor becomes nonzero. After several read operations, the accumulative net ﬂux disturbs the internal state significantly and result in soft errors. Thus, given a boundary of the mismatch between negative and positive pulse widths, a refreshing operation is needed to refresh the internal state after every speciﬁc number of read operations.

The recently proposed memristor-based memory array structure design used the crossbar structure [8]. In such crossbarbased memory structure, a diode in series with data storage cell is used as the selector of the cell. Such structure can works well for the unipolar memory cell. However, for a bipolar device as memristor, it is diﬃcult to provide a method to select a memristor in a crossbar array without disturbing the adjacent memristors, and such method can result in signiﬁcant leakage current for the memory array [12] [13]. Consequently, in our design, we follow the traditional memory structure and use MOSFET as the selector of the memory cells. However, this design methodology can be easily used in cross-bar based memristor memory array as long as the appropriate non-ohmic selector is discovered.

3. MEMRISTOR-BASED DUAL-ELEMENT MEMORY DESIGN

In this section, we ﬁrst characterize the power/energy consumption of a memristor cell. Based on our derivations, we propose a low-power dual-element memristor-based memory structure. The circuity for the dual-element memristorbased memory is also described.

3.1 The concept of dual-element memristor cell

One of the most distinguished features of memristor is that its internal state is only determined by the initial state (ω0) and the accumulated ﬂux (ϕ) applied to it, which is shown in Equation (4). Besides, Equation (2) shows that there is a one-to-one correspondence between the internal state (ω) and the memristance (M ). Therefore, from Equation (2) and Equation (4), the memristance of a cell is solely dependent on the ﬂux as:

M (ϕ) = (ξ1 − α0ξ2)2 − λξ2ϕ ,

(5)

Based on this observation, if a constant voltage, Vin, is applied to the memristor, the current-voltage relationship can be described as:

i(t) = Vin

,

(6)

(α0ξ2 − ξ1)2 − λξ2Vint

From the model presented in Equation (2), the lower bound and upper bound of the memristance are Rtop + Ron and Rtop + Roff . Thus Equation (6) is valid during the time

Programming Speed

1800

R=0.89(RHigh-Rlow) 1600

R=0.77(RHigh-Rlow)

1200

R=0.63(RHigh-Rlow)

800 T=0.50 R=0.71(RHigh-RLow)

R=0.44(RHigh-Rlow)

T=0.75 400 R=0.50(RHigh-RLow)

Resistance

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Time

Figure 2: Programming Time vs Resistance

interval of:

−2α0ξ1 + α02ξ2 < t < 2(1 − α0)ξ1 − (1 − α02)ξ2 . (7)

λVin

λVin

Otherwise, the currents are imax = Vin/(Rtop + Ron) and imin = Vin/(Rtop + Roff ), respectively.

Assuming that the programming time stays in the valid interval deﬁned in Equation (7), the power and energy consumption can be calculated as:

P (t) =

V2

√

in

(α0ξ2−ξ1)2−λξ2Vin t

E(t) = t P (x)dx

(8)

0

= 2λVξi2n ((ξ1 − α0ξ2) − (ξ1 − α0ξ2)2 − λξ2Vint )

Note that in Equation (8), the second part in the brackets has the same expression as the memristance shown in Equation (5), meaning that from the same state α0, the energy consumption is only determined by the ﬁnal memristance after the write operation. Therefore, if we do not use the whole range of the resistance, and only program a part of the memristor, the energy consumption can be saved remarkably. With this partial programming, the write pulse width is also reduced, and hence the write speed is increased. As shown in Fig. 2, the time for programming the cell from RHigh to 12 (RHigh − RLow) is reduced to 75% of the original time. On the other hand, if we program the cell from RLow, the programming time is reduced to 25%. Intuitively, programming the low resistant part of the memristor is faster than programming the high resistance part. Therefore, we can take advantage of this kind of “partial programming” to optimize the memristor-based memory.

One obvious limitation of partial programming is that the distinguishability of the memristor cell is reduced. The distinguishability of a memory cell is the ability to distinguish logic ‘0’ and logic ‘1’ during the read operation. For a memristor-based memory cell, the read operation is realized by applying a small voltage across the cell and then sensing the current through the cell. Since the magnitude of current is determined by the resistance of the memory cell, to ensure the reliability of the read operation, current accessing the cell should be distinguishable enough. As a result, the ratio of high resistance to low resistance can reﬂect the distinguishability between logic 0 and logic 1. For our memristor model, this ratio, RatioM can be calculated as:

RatioM = Rhigh = ξ1 . (9) Rlow ξ1 − ξ2

It is important to notice that RatioM is the physical parameter of a memristor cell and only determined by the storage

27

Vin

V Va a

Rx

Vref

Vout

Vin

V Va

a

Vb

b

Rx

Rx

Vout

(a)

(b)

Figure 3: Sense scheme for single-/dual-element memristor-based memory cell

material. If we also consider the sense scheme of the cell, which is shown in Fig. 3(a), the distinguishability of the cell is determined by the voltage gap applied to the sense ampliﬁer. Under an input voltage V , the voltage applied to the sense ampliﬁer is: Vout = VinRx/(Rx + Rcell). Given the high resistance Rhigh and low resistance Rlow, the series resistor Rx should be selected carefully to achieve the maximum voltage diﬀerence. This ‘optimal’ value of Rx is: Rx = RhighRlow. Therefore, the maximum voltage difference applied to the sense ampliﬁer, deﬁned as Λ, can be determined by:

Λ = Vin · Rhigh − Rlow . 2 (Rhigh + Rlow) + 2 RhighRlow

(10)

If partial programming is applied to the cell, both RatioM and Λ are reduced, which results in a degradation of the distinguishability of the cell. To overcome this disadvantage, a dual-element memristor-based memory is proposed. The basic idea of the dual-element memory cell is to use a pair of memristors to store the diﬀerential signals of the input data. During the write operation, the diﬀerential signals are saved in the cells separately. One of the cells, named the positive cell, stores the data with the same polarity of the input data, while the other one, negative cell, stores the complementary data. For example, in order to write logic ‘0’ into the cell, the positive cell is written to high resistance. At the same time, the negative cell is written to low resistance. The read scheme is diﬀerent from the general memristor memory proposed in [8]. As shown in Fig. 3(b), during the read operation, instead of comparing the voltage to a reference resistance, the voltages from the two memristors are compared. Therefore, the voltage gap input to the sense ampliﬁer is also increased. In order to obtain the same voltage gap, the memristor should be programmed to the statu that: Rint = RhighRlow. In this way, we can partial program each of the cell separately and use the associated information to achieve enough distinguishability.

3.2 Design space exploration

As mentioned above, the partial programming is faster than full programming. Also, the change of memristance is only determined by the ﬂux applied to the memristor. For energy optimization under a speciﬁc performance constraint, we can apply a low-magnitude long-width voltage pulse to program the cell. According to Equation (8), the energy consumed in the write operation is reduced as the input voltage decreases. On the other hand, one can also optimize the performance of the memory array under a speciﬁc energy constraint. Consequently, to design a dual-element memristor-based memory cell, the trade-oﬀs among speed, energy, and RatioM should be carefully explored. In order to

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explore the design space for dual-element memristor-based memory, the following constraint should be considered:

•RatioM or Λ should be above a minimum value to guarantee enough distinguishability for the whole cell;

• The programming voltage should not exceed a maximum voltage;

• For memristor, the read speed is much faster than write speed.Therefore, the operation speed mainly depends on the write speed. Thus, the write speed should be lower-bounded;

• Finally, the energy consumption for read and write a memory cell should not exceed certain power budget. Note in this paper, we assume the energy consumption is dominated by the write operation.

Consequently, three diﬀerent design optimization strategies can be applied for the proposed dual-element memristorbased memory: energy-driven, speed-driven or Rratio-driven design optimization. In this paper, due to the limited space, we focus on the energy-driven design optimization to implement a low-power memory cell. However, under other speciﬁcations such as high speed or high-distinguishability, the speed-driven or Rratio-driven optimization can be performed as well.

For the energy-driven optimization, the objective is to optimize the programming voltage Vin and pulse width tpulse to minimize the write energy consumption Ewrite, given the design requirements of Ratiomin, Λmin, Speedmin and Vmax. The design space of Vin and tpulse for the energy-driven optimization is shown in Fig. 4. Note, the partial programming from low resistant and high resistant side of the memristor consume diﬀerent amount of energy. Particularly, at the same speed and Rratio, programming from the high resistance side consumes more energy than from the low resistance. Also, the energy consumption increases with the increase of write speed. We should notice that, the upper and lower boundaries of write speed are restricted by the voltage constraints and noise immunity issues, which are denoted as Vmax and Vmin. Thus, for a low-power design, we should partially program the low resistance side of the memristor and program at the speed of Speedmin.

Based on the energy-driven optimization, a low-power dualelement memristor-based memory cell is proposed, which has the same speed and distinguishability as one cell memristorbased memory and consumes considerably less energy.

3.3 Memristor-based memory circuitry design

In this section, a dynamic memristor-based memory is proposed. This design can switch easily between a highcapability mode (normal mode) and a low-capability lowpower mode, with very small area and energy overhead compared to general memristor-based memory.

Fig. 5 shows the overall structure of the proposed memory array with peripheral circuits. Generally, the memory struc-

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Pselect Pulse Generator

Bank0

Mode Address

Word Line Decoder

Pselect Pulse Generator

Bank1

Sense Amplifier Sense Amplifier Mux

Figure 5: Overall structure of the memory array

+ Vin _

Mode Bit V1

R1

V2

Vref

Rx

R2 Rx

+_

SA1

+_

SA2

Vout1

Vout2

Figure 6: Circuit structure for dual-element memristor-based memory cell

ture is based on the design proposed in [8]. As mentioned, in order to avoid the problems due to the sneak paths, the MOSFET are used as the selector in our design. Moreover, we add several additional circuits to the design, ensuring that the memory can switch between the two modes. The memory is divided into two banks, bank 0 and bank 1. The positive cells are located in bank 0 and the negative cells are located in bank 1. Each bank has its own pulse generator. In Mode 0, two banks work independently, whereas in Mode 1, two banks work together to realize the dual-element memristor-based memory, and each pair of the associated cells are located at the same positions in every bank.

The pulse generator provide diﬀerent voltage levels to the memory cell. A mode bit is assigned to each pulse generator to choose the voltage level. If mode bit is logic ‘1’, indicating the memory works in low power mode, the low voltage VL is applied to memristor cells. If mode bit is logic ‘0’, the normal mode uses the high voltage VH for the circuit.

The read operation is similar to the single-cell memristor memory. As shown in Fig. 3, to extract the information of the cell, a voltage Vin is applied across the whole cell and the current is sensed. In Fig. 6, if the mode bit is set to 0, the circuit works as two independent memory cells. The voltage V1 and Vref are compared in sense ampliﬁer 1 (SA1). While V2 and Vref are compared in sense ampliﬁer 2 (SA2). However, if this bit is set to 1, the circuit works in lowpower dual-element mode. The resistors used to generate reference voltage are useless and are isolated. Additionally, the voltage V1 and V2 are compared to extract the data.

The modiﬁed word line decoder is illustrated in Fig. 7, which contains one traditional decoder and two block decoders. As mentioned, memristors in the dual-element cell locate in the same location of bank 0 and bank 1 respectively. For example, in Fig. 5, the memristors of address “0000” is associated with the memristors at “1000”. For each pair of

Address sn-1sn-2...s0

sn-2sn-3...s0

Word Line Decoder

w0

w1 w2 w3

word line of

block 0 w00

Block0

w01

Decoder

w02

w03

sn-1 Mode bit

w0 Mode Sn-1

0

0

1

0

1

1

X

0X

X

w00 w10 10 01 11 00

word line of

block 1

w10

Block1

w11

Decoder

w12

w13

Truth table of block decoder

Figure 7: Word line decoder for dual-element memristor-based memory cell

the associated memristor, only the ﬁrst bit of the address is diﬀerent. Thus, to decode the n bit address, a n-1 bit decoder is ﬁrstly used to decode the low n-1 bits of the address. After that, two word lines are selected at the same time. Then the highest bit and the mode bit are used together to generate the control signal for the two block decoders, deciding which line or both lines are activated. The truth table for the block decoder is shown in Fig. 7. If the Mode bit is 0, only one line is activated at one time, indicating the memory works at normal mode. Contrarily, if the Mode bit is 1, two word line are activated simultaneously.

4. EXPERIMENTAL RESULTS

4.1 Experiments setup

In our experiments, we model the memristor-based memory structure with 45nm CMOS technology (i.e., the memory storage cells are memristors while the peripheral circuitry are built with 45nm CMOS technology). The Synopsis HSPICE Tool with 45nm technology library is employed to get the delay, energy, and area values of the peripheral circuits of our memory design. Also, we use Cadence Spectre Analog environment to simulate the design of sense ampliﬁer. The memristor parameters and other memory parameters used in the experiments are shown in Table I [8] [11].

Table 1: Experiment Parameters

Parameters

Ron/Rof f Rtop µv L S

N1 /N2 W

Vw0 Vw1 Vr

Description Low/High Resistance Resistance of Upper Oxide

Equivalent dopants mobility Thin Film Thickness Cross section area Memory Size World Width Write level voltage at Mode 0 Write level voltage at Mode 1 Read voltage

Value 50/10K Ω 50 Ω 10−7m2/V · s 5nm 30nm × 30nm 32MB/16MB 8bits 1V 1/3V 1V

4.2 Energy Consumption Optimization

As mentioned in Section 3.2, to design the dual-element memory cell, a trade-oﬀ should be made among the energy, speed, and distingushiablility considerations. Three diﬀerent kinds of designs can be realized by using the dualelement memristor-based memory: energy-driven, speed-driven and Rratio/Λ-driven design. Our experiments mainly focus on the energy-driven optimization. However, we also show some ‘intermediate’ schemes of the optimization, which demonstrate the speed and distingushiablility improvements of the dual-element cell. For the energy-driven optimization, the problem can be formulated as following:

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Table 2: Diﬀerent Optimization Schemes

Scheme Resistance

Λ

Vwrite twrite Energy/Cell

Baseline Rl ∼ Rh

0.41V Vw0 25.38ns

3.20pJ

Scheme1 Rl ∼ Rh/2 0.74V Vw1 19.02ns

3.16pJ

Scheme2 Rl ∼ Rh/3 0.68V Vw1

8.85ns

2.10pJ

Scheme3 Scheme4

Rl ∼√Rh/4 Rl ∼ RlRh

0.63V 0.41V

Vw1 Vw1

4.98ns 0.78ns

1.54pJ 0.60pJ

Objective: Optimize the programming voltage Vin, and pulse width tpulse to minimize write energy Ewrite.

Constrains:

Λ > Λmin

Speedwrite > Speedmin Vmin < Vin < Vmax ,

(11)

According to the energy-driven optimization, four schemes of dual-element memristor-based memory cell are proposed, which are shown in Table. II. Baseline is the single-element memristor-based memory, in which the full range of the memristor is used. The other four schemes, scheme 1 to scheme 4, are the proposed dual-element memory with different resistance ranges and write strategies. Especially, Scheme 4 shows the most aggressive optimization of the design, which has the least resistance range and the equivalent distinguishability compared to the baseline scheme. Note that we use Λ and twrite as the design constraints in this paper to ensure the dual-element design has the comparable performance to the baseline design. Thus the design constraints are: Λ > Λbasline = 0.41V , twrite < tbaseline = 25.38ns , Vmax = 1V and Vmin = 1/3V . From this table, we can see that under these constraints, the proposed dual-element memristor-based memory can gain speed, distinguishability and energy improvement with diﬀerent design schemes. For example, Scheme 1 has the similar energy consumption as the baseline design. However, the distinguishability, denoted as Λ, increases from 0.41V to 0.74V. On the other hand, in the most aggressive scheme (scheme 4), the Λ is equal to Λbaseline. But the energy consumption is only about 18% of the baseline.

To study the eﬃciency of the proposed design, we compare the latency and energy consumption for two diﬀerent memory arrays, which are shown in Fig. 8. It is important to notice that the numbers of memristor used in the same size of memory are diﬀerent. For example, the baseline design of the 32MB memory has totally 32M × 8 memristors. However, the other schemes have 64M × 8 memristors. The results show that, although the proposed schemes use doubled number of memristors, the write energy and latency are improved signiﬁcantly. The energy consumption can be reduced by 40%, and the write latency can be improved by up to 90%.

5. CONCLUSION

In this paper, we perform a comprehensive study to analyze the power and energy consumption of the thin-ﬁlm memristor. A dual-element memristor-based memory structure is proposed, in which each memory cell contains two memristors that store the complement states. Our proposed design is veriﬁed through comprehensive simulation. The experimental results show that under the given design constraints, the proposed dual-element memory can achieve the same programming speed and distinguishability as the baseline single-element memory but the energy consumption can be reduced by up to 80%.

Reduction

100.00% 90.00% 80.00% 70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% -10.00%

32MB Memory Array

Baseline Scheme 1 Scheme 2 Scheme 3 Scheme 4

Read Latency Write Latency Read Energy Write Energy

Reduction

100.00% 90.00% 80.00% 70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% -10.00%

16MB Memory Array

Baseline Scheme 1 Scheme 2 Scheme 3 Scheme 4

Read Latency Write Latency Read Energy Write Energy

Figure 8: Comparison of latency/energy reduction

6. ACKNOWLEDGMENTS

This work was supported in part by NSF CAREER 0643902, 0916887, 0903432, and SRC grants. The author would like to acknowledge Xiangyu Dong from Penn State, Hai Li and Zhenyu Sun from NYU-Poly for their insightful discussions.

7. REFERENCES

[1] L. Chua. Memristor-the missing circuit element. IEEE Transactions on Circuit Theory, (5), Sep 1971.

[2] D. B. Strukov and et al. The missing memristor found. In Nature, 2008.

[3] Y. V. Pershin and M. D. Ventra. Experimental demonstration of associative memory with memristive neural networks. In Nature, 2009.

[4] H. Choi and et al. An electrically modiﬁable synapse array of resistive switching memory. Nanotechnology, 2009.

[5] Y. V. Pershin and M. D. Ventra. Practical approach to programmable analog circuits with memristors. Circuits and Systems I: Regular Papers, IEEE Transactions on, PP(99):1–8, 2010.

[6] Q. Yu and et al. Transmission characteristics study of memristors based op-amp circuits. ICCCAS, 2009.

[7] K. Witrisal. A memristor-based multicarrier uwb receiver. ICUWB, 2009.

[8] Y Ho, G. M. Huang, and P. Li. Nonvolatile memristor memory: device characteristics and design implications. In ICCAD, Nov. 2009.

[9] O. Kavehei and et al. The fourth element: Insights into the memristor. In ICCCAS, 2009.

[10] J. M. Tour and T. He. Electronics: The fourth element. In Nature, pages 42–43, 2008.

[11] R. Williams. How we found the missing memristor. IEEE Spectrum, (12), Dec. 2008.

[12] M. Dong and L. Zhong. Challenges to crossbar integration of nanoscale two-terminal symmetric memory devices. In NANO, pages 692 –694, Aug. 2008.

[13] H. Li and Y. Chen. An overview of non-volatile memory technology and the implication for tools and architectures. In DATE, 2009.

30

Dimin Niu†, Yiran Chen‡, Yuan Xie†

†Pennsylvania State University, University Park, PA ‡Seagate Technology, Bloomington, MN, USA †{dun118, [email protected]} ‡[email protected]

ABSTRACT

Recently, the emerging memristor device technology has attracted signiﬁcant research interests due to its distinctive hysteresis characteristic, which potentially can enable novel circuit designs for future VLSI circuits. In particular, characteristics such as non-volatility, non-linearity, low power consumption, and good scalability make memristor one of the most promising emerging memory technologies. Some important design parameter, however, such as speed, energy consumption, and distingushiablility, are mainly determined by the memristor’s physical characteristics. In this paper, a key observation of memristor’s asymmetric energy consumption is made by the detailed analysis of the transient power consumption. Based on this observation, we propose a dualelement memory structure in which each memory cell consists of two memristors. By constantly writing complement bits into the two elements within a cell, the dual-element is ﬂexible to satisfy design constraints which are usually diﬃcult to be satisﬁed with one-cell memory structure. Design space of the dual-element memory cell is studied and it shows that the trade-oﬀs among the energy, speed, and distingushiablility should be explored for diﬀerent design objectives. In particular, we show that under the energy-driven optimization, the proposed dual-element memory achieves the same programming speed and distinguishability as conventional single-element memory but the energy consumption can be reduced by up to 80%.

Categories and Subject Descriptors

B.7.1 [INTEGRATED CIRCUITS]: Types and Design Styles—Memory technologies

General Terms

Design, Measurement

Keywords

Memristor, Low Power, Nonvolatile Memory

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for proﬁt or commercial advantage and that copies bear this notice and the full citation on the ﬁrst page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior speciﬁc permission and/or a fee. ISLPED’10, August 18–20, 2010, Austin, Texas, USA. Copyright 2010 ACM 978-1-4503-0146-6/10/08 ...$10.00.

1. INTRODUCTION

Memristor, known as the fourth basic circuit element, was ﬁrst theoretically predicted by Chua in 1971 [1], and practically demonstrated by HP Labs in 2008 [2]. This emerging technology has many attractive features, including non-volatility, non-linearity, low-power, and good scalability. Such properties grant memristor the potential for innovations for future circuit and system architecture designs. For example, as memristor can accomplish most of the behaviors of the synapse such as remembering the past dynamic history and storing a continuous set of states, it has the potential to realize electronic neural networks [3] [4]. Some practical approaches of analog circuits with memristor have been proposed based on its non-linearity property [5] [6] [7]. In addition, non-volatility and good scalability make memristor a promising candidate as the next-generation highdensity, high-performance memory technology [8], and it has been predicted that memristor-based memory will be a strong competitor against other emerging memory technologies such as phase-change memory (PCRAM) and SpinTorque-Transfer Magnetic memory (STT-RAM) [8] [9].

For memory design, reducing the energy consumption is one of the most important design metrics for both high-end computing applications or low-end embedded applications. In this paper, we perform a comprehensive study to analyze the power and energy consumption of memristor-based memory design which adopts HP’s thin-ﬁlm memristor technology [2]. Based on the observations from our analysis, we propose a novel dual-element memristor based memory structure. In this novel structure, each memory cell contains two memristors, within which the complement bits are stored. During the read operation, the diﬀerential signals will be read out, and converted to logic ‘0’ or ‘1’. By writing complement bits into the two elements within a cell, the dual-element is ﬂexible to satisfy design constraints which usually cannot be achieved by one-cell memory structure. Design space of the dual-element is studied in this paper and it shows that a trade-oﬀ among the energy, speed, and distingushiablility should be explored for optimization of different objectives.

2. PRELIMINARIES

2.1 Memristor Model

The memristor is formally deﬁned as a two-terminal element in which the magnetic ﬂux between the terminals is a function of the amount of electric charge q that can pass through the device, which is explicitly expressed by the

25

Figure 1: Structure and model of memristor cell

equation dϕ = M dq, where M is called the memristance. If the relation is linear, memristance becomes constant and the memristor acts as a resistor. By contract, if it is non-linear, the memristance varies with the charge, which determines the hysteretic behavior of current/voltage proﬁle, and can be deﬁned as M (q). Generally, a memristive system can be described by the following relations:

V (t) = M (ω, i, t)I(t)

ω = f (ω, i, t) ,

(1)

where ω is the variable that indicates the internal state of the memristive system, V (t) and I(t) denote the voltage and current across the memristive system. Note, M is the memristance and depends on the system state, current, as well as time. If the memristance in Equation (1) only depends on the cumulative eﬀect of current, it becomes a charge dependent device, and is called a current-controlled memristor.

The structure of HP’s memristor cell is shown in Fig. 1(a) [2]. In this metal-oxide-metal structure, the top electrode and the bottom electrode are two thick metal wires on Pt, and two titanium dioxide ﬁlms are sandwiched by the electrodes. The upper titanium oxide is doped with oxygen vacancies, noted as T iO2−X , and has relatively high conductivity as a semiconductor. The lower oxide, which is perfect titanium oxide without dopants, has its natural state as an insulator. When a biased voltage is applied cross the thin ﬁlm, the oxygen vacancies are driven from the doped oxide to the undoped oxide and consequently lower the memristance of the whole cell. Contrarily, with a reversed bias voltage, the dopants migrate back to the doped oxide.

Based on the dopant drifting characteristics, the memristor can be modeled as a two-terminal device, which is made up of three resistors in series. Fig 1(b) shows the schematic of memristor model. The thicknesses of the upper and bottom oxides are Ltop and Lbtm, respectively. The upper oxide has a constant resistance of Rtop. But the resistance of the bottom oxide depends on the status of the oxide. We can denote the full undoped resistance as Roff and the full doped resistance as Ron. Obviously, Rtop, Ron, and Roff has the relationship as: Roff Ron, Roff Rtop, and Rtop/Ron = Ltop/Lbtm.

Since Rtop is a constant and relatively small, the total resistance is predominantly determined by the status of the bottom oxide. The state variable ω is deﬁned as the proportion of the length of the doped region to the total length of the bottom oxide, as shown in Fig. 1(b). Thus, the mathematical model for the memristance of the cell can be described by the resistances and the internal state ω as [2]:

M (ω) = Rtop + ωRon + (1 − ω)Roff ,

(2)

Under a biased voltage v(t), the length of the doping region

will change, which results in the change of the state variable ω. For example, a positive voltage causes the dopants (oxygen vacancies) to drift to the undoped region and therefore result in a lower memristance of the whole memristor. In the linear drift model, the boundary between the doped and undoped region drifts at a constant speed as: vdrift = µvRoni(t)/Lbtm. Based on this fact, the memristor can be modeled as [2]:

v(t) = (Rtop + ωRon + (1 − ω)Roff ) · i(t)

dω = µv ρTiO2−x i(t)

(3)

dt

LS

and the internal state (ω) can be deduced as:

ω(t) = ξ1 − (α0 − ξ1 )2 − λ ϕ(t) ,

(4)

ξ2

ξ2

ξ2

where ξ1 = Roff +Rtop, ξ2 = Roff −Ron, and λ = 2µvρ/LS. Also, α0 denotes the initial state of the memristor. Since the parameters ξ1, ξ2 and λ are constants and only depend on the material and manufacture process, the internal state ω can be considered as a ﬂux-driven variable. Accordingly, the memristance is determined by the ﬂux applied to it, regardless the waveform of the input voltage. Considering the ﬂux is the integral of voltage on time, if a square wave pulse is applied to the cell, the change of the memristance consequently depends on the pulse width of the input voltage. In this case, these properties make it suitable to employ memristor as a voltage-driven memory cell.

2.2 Memristor-based Memory

Attractive properties of the memristor such as non-volatility, high distinguishability, low-power, scalability and fast accessing speed make it a promising candidate for the nextgeneration high-density and high performance memory technology [8][10]. Consequently, memristor-based memory structure has been studied recently [8]. The basic structure of memristor-based memory is very similar to a typical memory array such as SRAM-based and DRAM-based memory, which consist of the word line decoder, memory array, sense ampliﬁer and output MUX. However, due to the special electronic characteristics of memristor, several additional peripheral circuits, such as pulse generator and R/W selector, should be added to implement the write/read operations. With the non-volatility and the ﬂux-driven properties, the key features for the memristor-based memory can be summarized as follows:

1) Information Storage: It has been reported that the oﬀ-to-on resistance ratios of HP’s memristor can achieve as much as 1000 [11], which implies a good distinguishability of the memristor-based memory. Since the memristance can reﬂect the internal state ω of the memristor, we can deﬁne the high resistance as logic ‘0’ and the low resistance as logic ‘1’. In addition, in the presence of noise, a safety margin should be deﬁned to ensure the reliability of the cell.

2) Write Operation: The write operation is to change the internal state of the memristor and therefore change the information stored in the cell. A simple way to write the memristor is to apply enough positive (writing logic ‘1’) or negative (writing logic ‘0’) voltage to the memristor cell. By applying a square wave pulse to the cell, the net ﬂux is only determined by the polarity and pulse width of the input

26

voltage. Thus, one can carefully adjust the input voltage to ensure the correct write operation.

3) Read Operation: The read operation is more complicated than the write. To read a memristor cell, a voltage is applied across the cell and the current is converted to voltage output by a sense ampliﬁer. Besides, in order to avoid the disturbing read and ensure the stabilization of the memristor’s internal state, a two-state read operation is proposed in [8]. The read pattern contains a negative pulse and a positive pulse with the same magnitude and duration, makeing sure zero net ﬂux is imported into the memristor cell.

4) Refresh Scheme: If the waveform of the read operation is not perfectly symmetrical, the net ﬂux applied to the memristor becomes nonzero. After several read operations, the accumulative net ﬂux disturbs the internal state significantly and result in soft errors. Thus, given a boundary of the mismatch between negative and positive pulse widths, a refreshing operation is needed to refresh the internal state after every speciﬁc number of read operations.

The recently proposed memristor-based memory array structure design used the crossbar structure [8]. In such crossbarbased memory structure, a diode in series with data storage cell is used as the selector of the cell. Such structure can works well for the unipolar memory cell. However, for a bipolar device as memristor, it is diﬃcult to provide a method to select a memristor in a crossbar array without disturbing the adjacent memristors, and such method can result in signiﬁcant leakage current for the memory array [12] [13]. Consequently, in our design, we follow the traditional memory structure and use MOSFET as the selector of the memory cells. However, this design methodology can be easily used in cross-bar based memristor memory array as long as the appropriate non-ohmic selector is discovered.

3. MEMRISTOR-BASED DUAL-ELEMENT MEMORY DESIGN

In this section, we ﬁrst characterize the power/energy consumption of a memristor cell. Based on our derivations, we propose a low-power dual-element memristor-based memory structure. The circuity for the dual-element memristorbased memory is also described.

3.1 The concept of dual-element memristor cell

One of the most distinguished features of memristor is that its internal state is only determined by the initial state (ω0) and the accumulated ﬂux (ϕ) applied to it, which is shown in Equation (4). Besides, Equation (2) shows that there is a one-to-one correspondence between the internal state (ω) and the memristance (M ). Therefore, from Equation (2) and Equation (4), the memristance of a cell is solely dependent on the ﬂux as:

M (ϕ) = (ξ1 − α0ξ2)2 − λξ2ϕ ,

(5)

Based on this observation, if a constant voltage, Vin, is applied to the memristor, the current-voltage relationship can be described as:

i(t) = Vin

,

(6)

(α0ξ2 − ξ1)2 − λξ2Vint

From the model presented in Equation (2), the lower bound and upper bound of the memristance are Rtop + Ron and Rtop + Roff . Thus Equation (6) is valid during the time

Programming Speed

1800

R=0.89(RHigh-Rlow) 1600

R=0.77(RHigh-Rlow)

1200

R=0.63(RHigh-Rlow)

800 T=0.50 R=0.71(RHigh-RLow)

R=0.44(RHigh-Rlow)

T=0.75 400 R=0.50(RHigh-RLow)

Resistance

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Time

Figure 2: Programming Time vs Resistance

interval of:

−2α0ξ1 + α02ξ2 < t < 2(1 − α0)ξ1 − (1 − α02)ξ2 . (7)

λVin

λVin

Otherwise, the currents are imax = Vin/(Rtop + Ron) and imin = Vin/(Rtop + Roff ), respectively.

Assuming that the programming time stays in the valid interval deﬁned in Equation (7), the power and energy consumption can be calculated as:

P (t) =

V2

√

in

(α0ξ2−ξ1)2−λξ2Vin t

E(t) = t P (x)dx

(8)

0

= 2λVξi2n ((ξ1 − α0ξ2) − (ξ1 − α0ξ2)2 − λξ2Vint )

Note that in Equation (8), the second part in the brackets has the same expression as the memristance shown in Equation (5), meaning that from the same state α0, the energy consumption is only determined by the ﬁnal memristance after the write operation. Therefore, if we do not use the whole range of the resistance, and only program a part of the memristor, the energy consumption can be saved remarkably. With this partial programming, the write pulse width is also reduced, and hence the write speed is increased. As shown in Fig. 2, the time for programming the cell from RHigh to 12 (RHigh − RLow) is reduced to 75% of the original time. On the other hand, if we program the cell from RLow, the programming time is reduced to 25%. Intuitively, programming the low resistant part of the memristor is faster than programming the high resistance part. Therefore, we can take advantage of this kind of “partial programming” to optimize the memristor-based memory.

One obvious limitation of partial programming is that the distinguishability of the memristor cell is reduced. The distinguishability of a memory cell is the ability to distinguish logic ‘0’ and logic ‘1’ during the read operation. For a memristor-based memory cell, the read operation is realized by applying a small voltage across the cell and then sensing the current through the cell. Since the magnitude of current is determined by the resistance of the memory cell, to ensure the reliability of the read operation, current accessing the cell should be distinguishable enough. As a result, the ratio of high resistance to low resistance can reﬂect the distinguishability between logic 0 and logic 1. For our memristor model, this ratio, RatioM can be calculated as:

RatioM = Rhigh = ξ1 . (9) Rlow ξ1 − ξ2

It is important to notice that RatioM is the physical parameter of a memristor cell and only determined by the storage

27

Vin

V Va a

Rx

Vref

Vout

Vin

V Va

a

Vb

b

Rx

Rx

Vout

(a)

(b)

Figure 3: Sense scheme for single-/dual-element memristor-based memory cell

material. If we also consider the sense scheme of the cell, which is shown in Fig. 3(a), the distinguishability of the cell is determined by the voltage gap applied to the sense ampliﬁer. Under an input voltage V , the voltage applied to the sense ampliﬁer is: Vout = VinRx/(Rx + Rcell). Given the high resistance Rhigh and low resistance Rlow, the series resistor Rx should be selected carefully to achieve the maximum voltage diﬀerence. This ‘optimal’ value of Rx is: Rx = RhighRlow. Therefore, the maximum voltage difference applied to the sense ampliﬁer, deﬁned as Λ, can be determined by:

Λ = Vin · Rhigh − Rlow . 2 (Rhigh + Rlow) + 2 RhighRlow

(10)

If partial programming is applied to the cell, both RatioM and Λ are reduced, which results in a degradation of the distinguishability of the cell. To overcome this disadvantage, a dual-element memristor-based memory is proposed. The basic idea of the dual-element memory cell is to use a pair of memristors to store the diﬀerential signals of the input data. During the write operation, the diﬀerential signals are saved in the cells separately. One of the cells, named the positive cell, stores the data with the same polarity of the input data, while the other one, negative cell, stores the complementary data. For example, in order to write logic ‘0’ into the cell, the positive cell is written to high resistance. At the same time, the negative cell is written to low resistance. The read scheme is diﬀerent from the general memristor memory proposed in [8]. As shown in Fig. 3(b), during the read operation, instead of comparing the voltage to a reference resistance, the voltages from the two memristors are compared. Therefore, the voltage gap input to the sense ampliﬁer is also increased. In order to obtain the same voltage gap, the memristor should be programmed to the statu that: Rint = RhighRlow. In this way, we can partial program each of the cell separately and use the associated information to achieve enough distinguishability.

3.2 Design space exploration

As mentioned above, the partial programming is faster than full programming. Also, the change of memristance is only determined by the ﬂux applied to the memristor. For energy optimization under a speciﬁc performance constraint, we can apply a low-magnitude long-width voltage pulse to program the cell. According to Equation (8), the energy consumed in the write operation is reduced as the input voltage decreases. On the other hand, one can also optimize the performance of the memory array under a speciﬁc energy constraint. Consequently, to design a dual-element memristor-based memory cell, the trade-oﬀs among speed, energy, and RatioM should be carefully explored. In order to

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explore the design space for dual-element memristor-based memory, the following constraint should be considered:

•RatioM or Λ should be above a minimum value to guarantee enough distinguishability for the whole cell;

• The programming voltage should not exceed a maximum voltage;

• For memristor, the read speed is much faster than write speed.Therefore, the operation speed mainly depends on the write speed. Thus, the write speed should be lower-bounded;

• Finally, the energy consumption for read and write a memory cell should not exceed certain power budget. Note in this paper, we assume the energy consumption is dominated by the write operation.

Consequently, three diﬀerent design optimization strategies can be applied for the proposed dual-element memristorbased memory: energy-driven, speed-driven or Rratio-driven design optimization. In this paper, due to the limited space, we focus on the energy-driven design optimization to implement a low-power memory cell. However, under other speciﬁcations such as high speed or high-distinguishability, the speed-driven or Rratio-driven optimization can be performed as well.

For the energy-driven optimization, the objective is to optimize the programming voltage Vin and pulse width tpulse to minimize the write energy consumption Ewrite, given the design requirements of Ratiomin, Λmin, Speedmin and Vmax. The design space of Vin and tpulse for the energy-driven optimization is shown in Fig. 4. Note, the partial programming from low resistant and high resistant side of the memristor consume diﬀerent amount of energy. Particularly, at the same speed and Rratio, programming from the high resistance side consumes more energy than from the low resistance. Also, the energy consumption increases with the increase of write speed. We should notice that, the upper and lower boundaries of write speed are restricted by the voltage constraints and noise immunity issues, which are denoted as Vmax and Vmin. Thus, for a low-power design, we should partially program the low resistance side of the memristor and program at the speed of Speedmin.

Based on the energy-driven optimization, a low-power dualelement memristor-based memory cell is proposed, which has the same speed and distinguishability as one cell memristorbased memory and consumes considerably less energy.

3.3 Memristor-based memory circuitry design

In this section, a dynamic memristor-based memory is proposed. This design can switch easily between a highcapability mode (normal mode) and a low-capability lowpower mode, with very small area and energy overhead compared to general memristor-based memory.

Fig. 5 shows the overall structure of the proposed memory array with peripheral circuits. Generally, the memory struc-

28

Pselect Pulse Generator

Bank0

Mode Address

Word Line Decoder

Pselect Pulse Generator

Bank1

Sense Amplifier Sense Amplifier Mux

Figure 5: Overall structure of the memory array

+ Vin _

Mode Bit V1

R1

V2

Vref

Rx

R2 Rx

+_

SA1

+_

SA2

Vout1

Vout2

Figure 6: Circuit structure for dual-element memristor-based memory cell

ture is based on the design proposed in [8]. As mentioned, in order to avoid the problems due to the sneak paths, the MOSFET are used as the selector in our design. Moreover, we add several additional circuits to the design, ensuring that the memory can switch between the two modes. The memory is divided into two banks, bank 0 and bank 1. The positive cells are located in bank 0 and the negative cells are located in bank 1. Each bank has its own pulse generator. In Mode 0, two banks work independently, whereas in Mode 1, two banks work together to realize the dual-element memristor-based memory, and each pair of the associated cells are located at the same positions in every bank.

The pulse generator provide diﬀerent voltage levels to the memory cell. A mode bit is assigned to each pulse generator to choose the voltage level. If mode bit is logic ‘1’, indicating the memory works in low power mode, the low voltage VL is applied to memristor cells. If mode bit is logic ‘0’, the normal mode uses the high voltage VH for the circuit.

The read operation is similar to the single-cell memristor memory. As shown in Fig. 3, to extract the information of the cell, a voltage Vin is applied across the whole cell and the current is sensed. In Fig. 6, if the mode bit is set to 0, the circuit works as two independent memory cells. The voltage V1 and Vref are compared in sense ampliﬁer 1 (SA1). While V2 and Vref are compared in sense ampliﬁer 2 (SA2). However, if this bit is set to 1, the circuit works in lowpower dual-element mode. The resistors used to generate reference voltage are useless and are isolated. Additionally, the voltage V1 and V2 are compared to extract the data.

The modiﬁed word line decoder is illustrated in Fig. 7, which contains one traditional decoder and two block decoders. As mentioned, memristors in the dual-element cell locate in the same location of bank 0 and bank 1 respectively. For example, in Fig. 5, the memristors of address “0000” is associated with the memristors at “1000”. For each pair of

Address sn-1sn-2...s0

sn-2sn-3...s0

Word Line Decoder

w0

w1 w2 w3

word line of

block 0 w00

Block0

w01

Decoder

w02

w03

sn-1 Mode bit

w0 Mode Sn-1

0

0

1

0

1

1

X

0X

X

w00 w10 10 01 11 00

word line of

block 1

w10

Block1

w11

Decoder

w12

w13

Truth table of block decoder

Figure 7: Word line decoder for dual-element memristor-based memory cell

the associated memristor, only the ﬁrst bit of the address is diﬀerent. Thus, to decode the n bit address, a n-1 bit decoder is ﬁrstly used to decode the low n-1 bits of the address. After that, two word lines are selected at the same time. Then the highest bit and the mode bit are used together to generate the control signal for the two block decoders, deciding which line or both lines are activated. The truth table for the block decoder is shown in Fig. 7. If the Mode bit is 0, only one line is activated at one time, indicating the memory works at normal mode. Contrarily, if the Mode bit is 1, two word line are activated simultaneously.

4. EXPERIMENTAL RESULTS

4.1 Experiments setup

In our experiments, we model the memristor-based memory structure with 45nm CMOS technology (i.e., the memory storage cells are memristors while the peripheral circuitry are built with 45nm CMOS technology). The Synopsis HSPICE Tool with 45nm technology library is employed to get the delay, energy, and area values of the peripheral circuits of our memory design. Also, we use Cadence Spectre Analog environment to simulate the design of sense ampliﬁer. The memristor parameters and other memory parameters used in the experiments are shown in Table I [8] [11].

Table 1: Experiment Parameters

Parameters

Ron/Rof f Rtop µv L S

N1 /N2 W

Vw0 Vw1 Vr

Description Low/High Resistance Resistance of Upper Oxide

Equivalent dopants mobility Thin Film Thickness Cross section area Memory Size World Width Write level voltage at Mode 0 Write level voltage at Mode 1 Read voltage

Value 50/10K Ω 50 Ω 10−7m2/V · s 5nm 30nm × 30nm 32MB/16MB 8bits 1V 1/3V 1V

4.2 Energy Consumption Optimization

As mentioned in Section 3.2, to design the dual-element memory cell, a trade-oﬀ should be made among the energy, speed, and distingushiablility considerations. Three diﬀerent kinds of designs can be realized by using the dualelement memristor-based memory: energy-driven, speed-driven and Rratio/Λ-driven design. Our experiments mainly focus on the energy-driven optimization. However, we also show some ‘intermediate’ schemes of the optimization, which demonstrate the speed and distingushiablility improvements of the dual-element cell. For the energy-driven optimization, the problem can be formulated as following:

29

Table 2: Diﬀerent Optimization Schemes

Scheme Resistance

Λ

Vwrite twrite Energy/Cell

Baseline Rl ∼ Rh

0.41V Vw0 25.38ns

3.20pJ

Scheme1 Rl ∼ Rh/2 0.74V Vw1 19.02ns

3.16pJ

Scheme2 Rl ∼ Rh/3 0.68V Vw1

8.85ns

2.10pJ

Scheme3 Scheme4

Rl ∼√Rh/4 Rl ∼ RlRh

0.63V 0.41V

Vw1 Vw1

4.98ns 0.78ns

1.54pJ 0.60pJ

Objective: Optimize the programming voltage Vin, and pulse width tpulse to minimize write energy Ewrite.

Constrains:

Λ > Λmin

Speedwrite > Speedmin Vmin < Vin < Vmax ,

(11)

According to the energy-driven optimization, four schemes of dual-element memristor-based memory cell are proposed, which are shown in Table. II. Baseline is the single-element memristor-based memory, in which the full range of the memristor is used. The other four schemes, scheme 1 to scheme 4, are the proposed dual-element memory with different resistance ranges and write strategies. Especially, Scheme 4 shows the most aggressive optimization of the design, which has the least resistance range and the equivalent distinguishability compared to the baseline scheme. Note that we use Λ and twrite as the design constraints in this paper to ensure the dual-element design has the comparable performance to the baseline design. Thus the design constraints are: Λ > Λbasline = 0.41V , twrite < tbaseline = 25.38ns , Vmax = 1V and Vmin = 1/3V . From this table, we can see that under these constraints, the proposed dual-element memristor-based memory can gain speed, distinguishability and energy improvement with diﬀerent design schemes. For example, Scheme 1 has the similar energy consumption as the baseline design. However, the distinguishability, denoted as Λ, increases from 0.41V to 0.74V. On the other hand, in the most aggressive scheme (scheme 4), the Λ is equal to Λbaseline. But the energy consumption is only about 18% of the baseline.

To study the eﬃciency of the proposed design, we compare the latency and energy consumption for two diﬀerent memory arrays, which are shown in Fig. 8. It is important to notice that the numbers of memristor used in the same size of memory are diﬀerent. For example, the baseline design of the 32MB memory has totally 32M × 8 memristors. However, the other schemes have 64M × 8 memristors. The results show that, although the proposed schemes use doubled number of memristors, the write energy and latency are improved signiﬁcantly. The energy consumption can be reduced by 40%, and the write latency can be improved by up to 90%.

5. CONCLUSION

In this paper, we perform a comprehensive study to analyze the power and energy consumption of the thin-ﬁlm memristor. A dual-element memristor-based memory structure is proposed, in which each memory cell contains two memristors that store the complement states. Our proposed design is veriﬁed through comprehensive simulation. The experimental results show that under the given design constraints, the proposed dual-element memory can achieve the same programming speed and distinguishability as the baseline single-element memory but the energy consumption can be reduced by up to 80%.

Reduction

100.00% 90.00% 80.00% 70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% -10.00%

32MB Memory Array

Baseline Scheme 1 Scheme 2 Scheme 3 Scheme 4

Read Latency Write Latency Read Energy Write Energy

Reduction

100.00% 90.00% 80.00% 70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% -10.00%

16MB Memory Array

Baseline Scheme 1 Scheme 2 Scheme 3 Scheme 4

Read Latency Write Latency Read Energy Write Energy

Figure 8: Comparison of latency/energy reduction

6. ACKNOWLEDGMENTS

This work was supported in part by NSF CAREER 0643902, 0916887, 0903432, and SRC grants. The author would like to acknowledge Xiangyu Dong from Penn State, Hai Li and Zhenyu Sun from NYU-Poly for their insightful discussions.

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