SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY Master of Technology

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SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY Master of Technology

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SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY
(A Constituent College of Sri Siddhartha Academy of Higher Education)
Master of Technology in DIGITAL ELECTRONICS 2020-21 Batch
I Semester

Subject Code

Subject

DEL101 DEL102 DEL103 DEL104 DEL15Y DEL106 DEL107

Digital Circuits and Logic Design CMOS VLSI design
Advanced Embedded System Digital Image Processing
Elective-I Technical Seminar - I Embedded Systems lab
Total Credits

L – T – P – C
4 - 0 - 0 - 4 4 - 0 - 0 - 4 4 - 0 - 0 - 4 4 - 0 - 0 - 4 4 -0 - 0 - 4 0 - 0 - 0 - 2 0 - 0 - 3 - 1
20 -0 – 3 - 23

Marks for

CIE SEE Total

50 100 150

50 100 150

50 100 150

50 100 150

50 100 150

50

--

50

50

--

50

350 500 850

Elective I: DEL151: Research Methodology and IPR DEL152: Advanced Computer Architecture DEL153: Nano Electronics
*Y stands for numerals 1,2,3..

II Semester

Subject Code

Subject

DEL201 DEL202
DEL203
DEL204 DEL25Y DEL206 DELL207

Modern DSP Synthesis & optimization of Digital Circuits Micro Electro Mechanical Systems
Real Time Embedded System Elective-II Technical Seminar-II
Modern DSP Lab
Total Credits

L – T – P – C
4 - 0 - 0 - 4 4 - 0 - 0 - 4
4 - 0 - 0 - 4
4 - 0 - 0 - 4 4 -0 - 0 - 4 0 - 0 - 0 - 2 0 - 0 - 3 - 1
20 -0 – 3 - 23

Marks for CIE SEE Total 50 100 150 50 100 150

50 100 150

50 100 150

50 100 150

50

--

50

50

--

50

350 500 850

Elective II:
DEL251: Digital System Design using Verilog DEL252: DSP Integrated Circuits DEL253: Neural networks and Fuzzy logic

*Y stands for numerals 1,2,3..

III Semester

Subject Code

Subject

DEL301 DEL302

Internship Project work Phase-I
Total Credits

L – T – P – C
0 - 0 - 0 - 10 0 - 0 - 0 - 09
19

Marks for

CIE SEE Total

100

100

50

50

150

150

Note: DEL301: Internship: Report evaluation on Internship (50 Marks)
Viva – Voce and Evaluation of Internship (50 Marks)
DEL302: Project Work Phase-I: Literature Survey to finalize the topic of the project and presentation of the same (50 Marks)

IV Semester

Subject Code

Subject

DEL41Y DEL42Y DEL403

Elective-III Elective-IV
Project work Phase-II
Total Credits

L – T – P – C
4 - 0 - 0 - 4 4 - 0 - 0 - 4 0 - 0 - 0 - 15 8 – 0 – 0 - 23

Marks for
CIE SEE Total 50 100 150 50 100 150 100 200 300 200 400 600

Elective-III Elective VI DEL411:Reliability Engineering DEL412: RF Microelectronics chip design DEL413:Memory Technologies

DEL421: Internet of Things DEL422: Deep Learning DEL423: Ad-hoc and WSN

*Y stands for numerals 1,2, 3.

Note: Project Work Phase-II:
1.
2.
3.

Project work Seminar – I: Presentation of the project work carried out for the first six weeks (50 Marks)
Project work Seminar – II: Presentation of the project work carried out for the next eight weeks (50 Marks)
Project work evaluation taken up at the end of the IV semester.  Report Evaluation: Average of the marks evaluated by internal and
external examiners (125 Marks)  Viva- Voce: Conducted and evaluated jointly by internal and
external examiners (75 Marks)

Total Credits (I to IV Semester)

88

Total Marks (I to IV Semester)

2450

Program Objectives:

An ability to independently carry out research /investigation and development P01 work to solve practical problems.

PO2

An ability to write and present a substantial technical report/document.

Students should be able to demonstrate a degree of mastery over the area as per the PO3 specialization of the program. The mastery should be at a level higher than the
requirements in the appropriate bachelor program.

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY- TUMAKURU
(A constituent College of Siddhartha Academy of Higher Education, Tumakuru)

Department of Electronics and Communication M.Tech in Digital Electronics
Syllabus for the Academic Year – 2020 - 2021

Semester: I

Subject Name: Digital Circuits and Logic Design

Subject Code: DEL101

L – T – P – C: 4-0-0-4

Course Objectives:

Sl.No Course Objectives
The objective of this subject is to explore students to advanced concepts of design, simplify, testing and debug 1 of digital circuits using prior knowledge of logic design and advanced logic design concepts

Course Outcomes

Course outcome
CO1
CO2
CO3 CO4

Descriptions
Apply the concepts and laws of logic design to solve logical problems(L3) Solve complexity of logical equation using simplification techniques and decomposition methods(L4) Design logical circuits such as encoder, decoder, sine wave.(L3) Test the digital circuit for faults and design fault free circuit(L3)

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY- TUMAKURU
(A constituent College of Siddhartha Academy of Higher Education, Tumakuru)

SYLLABUS

UNIT I
II III IV V

Description Review Of Digital Concepts: Problem statement to truth tables, combinational logic, logic problems simplification of Boolean functions, Kmap, Quine-McCluskey method, Map entered variable. Logic design: Analysis of combinational circuits, comparators, data selectors, Encoders – priority encoder, Decoders – BCD to Decimal, seven segment display, Sine generators, Design of high-speed adders – Ripple adder, Carry look ahead adder. Functional Decomposition And Symmetric Functions: Functional Decomposition, Decomposition by expansion, Test for decomposability, Decomposition charts, Symmetric networks, Properties ofsymmetric functions, synthesis, complemented variables of symmetry, Identification of symmetric functions. Reliable Design And Fault Diagnosis Hazards: Fault Detection in Combinational Circuits, Fault-Location Experiments, Boolean Differences, Fault Detection by Path Sensitizing, Detection of Multiple Faults, FailureTolerant Design, Quadded Logic. Introduction To Synchronous Sequential Circuits And Iterative Networks: Sequential circuits- The finite state model- Memory element and their excitation functions, Synthesis of synchronous sequential circuits, Iterative networks. Capabilities, Minimization, And Transformation Of Sequential Machines: The Finite- State Model, Further Definitions, Capabilities and Limitations of Finite – State Machines, Equivalence and Machine Minimization, Simplification of Incompletely Specified Machines. Structure of Sequential Machines: State Assignments Using Partitions, The lattice of closed partitions, Reduction of the output dependency, Input independence and autonomous clocks.

Hours 14Hrs
7Hrs 8Hrs 9Hrs 14Hrs

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY- TUMAKURU
(A constituent College of Siddhartha Academy of Higher Education, Tumakuru)

Text Books:

Sl No 1

Title Switching and Finite
Automata Theory

2

Fundamentals of Logic

Systems

Authors ZviKohavi
Charles Roth Jr

Volume and Year of Edition
2nd Edition. Tata McGraw Hill Edition, ISBN-10: 0-07-099387-4
Cengage learning, 7th edition, 2013, ISBN-13: 978-1133628477

Reference Books:
Sl Title No
Fault Tolerant and fault testable 1
hardware design
2 Introductory theory of computer

Authors Parag K Lala V. Krishnamurthy

3 Theory of computer science – Automata, Mishra &

Languages and Computation

Chandrasekaran

Volume and Year of Edition Prentice Hall Inc. 1985
Macmillan Press Ltd, 1983
2nd Edition, PHI, 2004

Department of Electronics and Communication

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY- TUMAKURU
(A constituent College of Siddhartha Academy of Higher Education, Tumakuru)

M.Tech in Digital Electronics Syllabus for the Academic Year – 2020 - 2021
Semester: I Subject Name:CMOS VLSI DESIGN

Subject Code: DEL102

L – T – P – C: 4-0-0-4

Course Objectives:
Sl.No Course Objectives To make the students learn the principles, operations and applications of
1 MOSFET’s.
To introduce the students to modelling and design of digital VLSI circuits 2 using different CMOS design styles and CMOS sub system.
To make the students learn stick diagrams and layouts using Lambda based 3 design rules for a given schematic and to categorize the different MOS
technologies

Course Outcomes

Course Descriptions outcome

CO1

Identify the different design techniques used in modeling the digital VLSI Circuits. (L1)

CO2

Calculate the design parameters for the CMOS circuits and can estimate the parasitic values for different mask layers. (L2)

CO3 Outline the MOS process technology and CMOS sub system design. (L4)

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY- TUMAKURU
(A constituent College of Siddhartha Academy of Higher Education, Tumakuru)

SYLLABUS

UNIT I
II

Description Unit 1: MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage equation, body effect, MOS device design equation, sub threshold region, Channel length modulation. mobility variation, Tunneling, punch through, hot electron effect MOS models, small signal AC Characteristics, CMOS inverter, βn / βp ratio, noise margin, static load MOS inverters, differential inverter, transmission gate, tristate inverter, BiCMOS inverter. (Text1) Unit 2: CMOS Process Technology Silicon Semiconductor technology: An overview, basic CMOS technology. A basic n-well CMOS process, The p-well process, twin tub process, silicon on insulator. (Text1) CMOS process enhancements: Interconnect, circuit elements; Resistors, Capacitors, bipolar transistors, Thin film transistors,3DCMOS (Text1) MOS Design Processes: MOS layers, stick diagrams, design rules and layout, symbolic diagrams. (Text3)

Hours 12
10

Unit 3: Basic circuit concepts: Sheet resistance, standard unit of capacitance

concepts, delay unit time inverter delays, driving capacitive loads, propagation

III delays, scaling of MOS circuits (Text3)

10

Basics of Digital CMOS Design: Combinational MOS Logic circuits-

Introduction, MOS logic circuits with depletion NMOS load. (Text2)

Unit 4: Basics of Digital CMOS Design:Contd.. CMOS logic circuits,

complex logic circuits, CMOS Transmission Gate. (Text2)

10

IV Sequential MOS logic Circuits : Introduction, Behavior of bi stable elements,

SR latch Circuit, (Text2).

Unit 5:Sequential MOS logic Circuits :Contd..

Clocked latch and Flip Flop Circuits, CMOS D- latch and triggered Flip Flop

(Text2).

10

Dynamic CMOS and clocking: Introduction, advantages of CMOS over V NMOS, CMOS\SOS technology’ CMOS\bulk technology, latch up in bulk

CMOS, static CMOS design, Domino CMOS structure and design, Charge

sharing, Clocking- clock generation, clock distribution, clocked storage

elements. (Text5)
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