About the International Technology Roadmap for Semiconductors

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About the International Technology Roadmap for Semiconductors

Transcript Of About the International Technology Roadmap for Semiconductors

Welcome !
Thank you for your interest in the International Technology Roadmap for Semiconductors: 1999 edition.
We have worked diligently as teams of Technology Working Groups from around the world to assess technology requirements for the semiconductor industry over the next 15 years. The working groups include the technologies of Design; Test and Test Equipment; Process Integration, Devices, and Structures; Front-end Processes; Lithography; Interconnect; Factory Integration; Assembly and Packaging; Environment, Safety, and Health; Defect Reduction; Metrology; and Modeling and Simulation.
For this edition, our focus has been on near term needs for the next six years, and then assessing the longer term issues in the years beyond 2005. We see technical opportunities as well as challenges for all areas as the industry approaches the 100 nm feature size realm and beyond.
As we continue to assess where we are and where we are going, we are once again humbled at the scope of this exercise of “roadmapping” our industry’s needs in the areas of research and development. This is an ongoing process as new innovations surface throughout the world, requiring constant review and routine revisions of this information.
This effort is sponsored by the Semiconductor Industry Association (SIA), and with participation from members of the European Electronic Component Association (EECA), the Electronic Industries Association of Japan (EIAJ), the Korea Semiconductor Industry Association (KSIA), and the Taiwan Semiconductor Industry Association (TSIA).
About the International Technology Roadmap for Semiconductors
The semiconductor industry consists of a global community of suppliers, researchers, and chip manufacturers. The Semiconductor Industry Association's (SIA) 1994 and 1997 editions of the National Technology Roadmap for Semiconductors were very valuable to this world wide industry. The community has responded to the recommendations of the Roadmap for continuing success. It is understood, however, the industry needs for research and development are constantly changing, requiring frequent reviews and new assessments. It is recognized that these assessments that include the entire community leverages our understanding of key challenges we all face as an industry.
As such, the Technology Roadmap for Semiconductors is always in active review. The year 1999 is a formal revision year for the Roadmap. The Technology Working Groups (TWGs) assess the data for technology needs and areas where innovation is encouraged. By consensus these teams update the information. ITRS conferences provide a forum for review by the entire semiconductor community for feedback and input.
Once this feedback is gathered, each TWG issues a formal report. These reports make up the Roadmap. The Roadmap is then reviewed and approved by technical advisory boards from all over the world, prepared for distribution, and made available to the public.
We invite you to participate in this dynamic process by coming to the ITRS Conferences to promote continued success of the industry!
Special thanks to members of the European Electronic Component Association (EECA), the Electronic Industries Association of Japan (EIAJ), the Korea Semiconductor Industry Association (KSIA), and the Taiwan Semiconductor Industry Association (TSIA) for their valued input.
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TECHNOLOGYNODE (nm)—The ground rules of process governed by the smallest feature printed. The half-pitch of firstlevel interconnect dense lines is most representative of the DRAM technology level required for the smallest economical chip size. For logic, such as microprocessors (MPUs), gate length is most representative of the leading-edge technology level required for maximum performance. MPU and ASIC logic interconnect half-pitch processing requirements typically lag behind DRAM half-pitch. For cost reasons, high-volume, low-cost ASIC gate-length requirements will typically match DRAM half-pitch targets, but the low-volume leading-edge high-performance ASIC gate-length requirements will track closely with MPUs.
“MOORE’S LAW”—An historical observation by Intel executive, Gordon Moore, that the market demand (and semiconductor industry response) for functionality per chip (bits, transistors) doubles every 1.5 to 2 years. He also observed that MPU performance [clock frequency (MHz) × instructions per clock = millions of instructions per second (MIPS)] also doubles every 1.5 to 2 years. Although viewed by some as a “self-fulfilling”prophecy,“Moore's Law” has been a consistent macro trend, and key indicator of successful leading-edge semiconductor products and companies, for the past 30 years.
“COST-PER-FUNCTION”MANUFACTURINGPRODUCTIVITY IMPROVEMENT DRIVER—In addition to“Moore’s Law”, there is a historically-based “corollary” to the “law,” which suggests that, to be competitive, manufacturing productivity improvements must also enable the cost-per-function (microcents per bit or transistor) to decrease by -29% per year. Historically, when functionality doubled every 1.5 years, then cost-per-chip (packaged unit) could double every six years and still meet the cost-per-function reduction requirement. If functionality doubles only every two years, as suggested by consensus DRAM and MPU models of the 1999 ITRS, then the manufacturing cost per chip (packaged unit) must remain flat.
“Affordable” Packaged Unit Cost/Function—Final cost in microcents of the cost of a tested and packaged chip divided by Functions/Chip. Affordable costs are calculated from historical trends of affordable average selling prices [gross annual revenues of a specific product generation divided by the annual unit shipments] less an estimated gross profit margin of approximately 35% for DRAMs and 60% for MPUs. The affordability per function is a guideline of future market “tops-down” needs, and as such, was generated independently from the chip size and function density. Affordability requirements are expected to be achieved through combinations of—1) smaller chip sizes from technology and design improvements; 2) increasing wafer diameters; 3) decreasing equipment cost-of-ownership (CoO); 4) increasing equipment overall equipment effectiveness; 5) reduced package and test costs; 6) improved design tool productivity; and 7) enhanced product architecture and integration.
DRAMGeneration at (product generation life-cycle level)—The anticipated bits/chip of the DRAM product generation introduced in a given year, manufacturing technology capability, and life-cycle maturity (Demonstration, Introduction, Sample, Production, Ramp, Peak).
MPU Generation at (product generation life-cycle level)—The generic processor generation identifier for the anticipated Microprocessor Unit (MPU) product generation functionality (logic plus SRAM transistors per chip) introduced in a given year, manufacturing technology capability, and life-cycle maturity (Introduction, Ramp, Peak, Embedded).
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There will be a number of problems in scaling the basic MOSFET structures, particularly for the 100 nm technology node and beyond. The most pressing of these is with the gate stack, the combination of gate dielectric and electrode. The reason for this problem is the thin oxide thickness required for 110 nm and beyond technology generations. For such thin oxides, the gate leakage current due to direct tunneling would become unacceptably large. Use of alternate gate dielectrics with higher relative dielectric constant (κ) than silicon dioxide is the leading projected solution to reduce the gate leakage current to more tolerable levels. However, the time to develop and implement such dielectrics in production is exceedingly short, since the 110 nm node is scheduled for first production by 2004. This is the highest risk problem in the front end. Along with high κ gate dielectrics, dual metal for the gate electrodes is a potential solution to eliminate depletion effects in polysilicon gates and the problem of boron penetration from P+ polysilicon. Also, metal electrodes sharply reduce the gate resistance and avoid the problem that occurs with silicided polysilicon of increasing sheet resistance for very narrow gates. Ultra-shallow source/drain (S/D) extension junctions will be required, and techniques such as plasma assisted implantation, projection gas immersion laser doping, and ultra-low energy (< 0.5keV) implants are projected solutions for fabricating these junctions. In the deep S/D contact, the requirement of low sheet resistance and contact resistance and shallow junction depth will become increasingly difficult to meet without such innovations as raised S/D or epitaxial Si/Ge. Finally, to maintain the on current and deal with short-channel effects, advanced channel engineering techniques such as highly optimized halo implants and the use of high mobility silicon/germanium epitaxial layers are envisioned. Refer to Figure 13 for the Memory and Logic potential solutions.
Even with innovative scaling solutions as discussed above, it will be quite difficult with technologies at the 100 nm node and beyond to simultaneously meet the requirements for Ion, Ioff , and limited overall chip power dissipation. This is due to the sharp scaling of Vdd, while the threshold voltage, Vt, must remain relatively constant to keep Ioff within tolerable limits. Using multiple Vts on the chip, or switched Vt through well bias (which requires triple well for bulk CMOS), or dynamic Vt, where the Vt is changed by the gate bias, could alleviate these problems. (Dynamic Vt requires that Vdd ≤ 0.6 V to avoid excessive junction leakage due to forward biasing of the source/substrate junction.) Also, SOI technology, with its high-performance at low Vdd and its low parasitic capacitance, could be an important solution. Eventually, for the 50 nm node or beyond, such novel structures as dual gate SOI or vertical MOSFETS may be needed. Even further out, novel switching devices such as quantum dot or single electron transistors, are possible solutions. More accurate, comprehensive, and easy to use TCAD and modeling tools are needed to develop and implement the abovementioned solutions in a cost-effective, timely manner.
For interconnect, as the technology is scaled and the speed increases, the number of metal levels and the density of the wiring increases and reduction of the parasitic resistance and capacitance becomes critical. Copper is being implemented in current technology by some companies because of its relatively low resistivity and its high lifetime against electromigration. Eventually, copper is expected to replace aluminum as the mainstream metallization for ICs. Low dielectric constant (κ) materials are also being implemented for the interlevel and intralevel dielectric to reduce the capacitance, and it is expected that newer materials with lower κ will be utilized for later technology generations. Eventually, “void” structures such as air gap, void-based materials, etc., may be implemented. It is expected that the combination of copper and low κ dielectrics will suffice for many technology generations. In the long run, however, beyond the 50 nm technology node, highly innovative solutions such as optical interconnect, liquid nitrogen cooled conductors, may be utilized to overcome the inherent speed and power limitations of copper and low κ dielectrics.
For DRAMs, improvements in density, cost, speed, and noise immunity with scaling are critical. As with the gate dielectric, high κ dielectrics are expected to be implemented to increase the capacitance of the storage nodes. Also, similar low κ dielectrics to those in logic IC interconnects will be implemented to lower the
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confine charge and provide current conduction without loss. Inventive new device architectures and concepts are required to address these end-of-roadmap needs.
The use of DRAMs has proliferated because of extraordinary reductions in cost per bit, in part achieved by the ability to scale the size of the DRAM storage cell at a rate that is greater than the square of the DRAM half-pitch dimension. This has resulted in a historical doubling of on-chip bit density every two years. Such aggressive scaling has been accomplished through the utilization of inventive storage cell configurations that make efficient use of chip area. Throughout this period, the storage cell capacitor dielectric has remained silicon oxide or a nitride derivative. However, further aggressive scaling will require that the limited dielectric constant afforded by these materials has resulted in the need to replace these dielectrics with a material of much higher dielectric constant. Changes in capacitor electrodes will also be required to effect this change. It is unlikely that the high κ and electrode materials chosen for this application will be the same as those chosen for the MOSFET gate dielectric because, aside from the common need for high dielectric constant, the other requirements are different. As a result, it is likely that a new fabrication process for either the present stack or trench capacitor structures will be required. This new fabrication process poses problems of equivalent complexity and scope as those associated with the future CMOS gate stack, and the timeline for manufacturing deployment are very similar. Therefore, it is anticipated that industry resources of equivalent scope will be required to address this conversion.
The nature of these challenges are detailed in Table 31 as well as in the text, tables, and figures in the following portions of this chapter.

Table 31 Front End Process Difficult Challenges



Nitride Derivatives and High κ Gate Stacks

Effective oxide thickness ~/>1.2 nm for nitride derivatives, ~/< 1.2 nm for high κ

DRAM Storage Cells (Stack and Trench Capacitors)
Ultra-Shallow Junctions (USJ) with Standard Processing
Leff Control
Met r ology

Achieve optimal channel mobility >95% of SiO2 Minimize gate leakage mechanisms to achieve ~/<1A/cm2 for
high-performance logic and ~/<0.001 A/cm2 for system LSI Control Boron penetration. Minimize gate electrode depletion, e.g., polysilicon depletion Chemical compatibility of dual metal with appropriate work
Implementation of Ta2O5, BST, etc., with associated compatible electrode materials
Capacitor structures that meet (DRAM ½ Pitch)2 scaling Trench and stack capacitor scaling to <100 nm Achievement of lateral and depth abruptness
Achievement of low series resistance, <10% of channel Rs Annealing technology to achieve ~/<300Ω/ at ~/<30 nm Xj Etch CD control and selectivity Sidewall etch control Microloading effects of dense/isolated lines Halo/pocket implant optimization Overall thermal cycle control Physical, electrical and chemical measurement and
characterization of gate dielectric, electrodes, USJ , etc.

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Year Technology Node

1999 180 nm

2002 130 nm

2005 100 nm

2008 70 nm

2011 50 nm

2014 35 nm

Upper Electrode (A)
High κ Dielectric Bottom Electrode (A,B)

poly-Si TiON




Ta O






super high κ tbd

(A) Metal : W, Pt, Ru, RuO2, IrO2
(B) Perovskite : SrRuO3
Figure 22 DRAM Stack Capacitor Films Potential Solutions
Table 36 summarizes the technology requirements for DRAM trench capacitor technology. The target values are based on the assumption of a 35fF capacitance per DRAM cell. For storage nodes down to, and including the 100 nm technology node, trench capacitor technology is characterized by conventional thickness scaling of the NO capacitor dielectric, in combination with surface enhancement techniques such as bottle-shaped trenches. As a result of ground-rule shrinking, the aspect ratio (trench depth to trench width) will increase up to values of ~60 for the 100 nm technology node. It is expected that a new high κ dielectric material will not be required before the 70 nm technology node.
For embedded applications, the trench technology with its capacitor buried in the substrate, enables a planar transition between the DRAM cell array and the logic circuit. Thus, a critical thinning of individual metal lines of the multilevel metallization, or reduced lithographic resolution at the transition area is avoided. Also avoided is the need for deep, high aspect ratio contact holes. In addition, since the capacitor is processed prior to the transfer device, degradation of device performance from the capacitor-forming thermal cycle is not encountered.
The scaling of the cell area factors as a consequence of the new chip size model will require a further optimization of the layout and the areas consumed by each element of the DRAM storage cell. This implies measures such as the replacement of the conventional planar transfer device by a vertical transistor, or the reduction in storage node area by further increases in the aspect ratio of the capacitor structure. Finally, all current DRAM technologies with their lithographic defined wordline, and bitline pitch, will reach a theoretical scaling limit at a cell size of 4F2 given by the 2F pitch for each metal line. For smaller values, new concepts such as multi-bit circuits or multi-layer DRAMs are required. No currently known solutions exist for such fundamental changes.

30 N. Fukushima, et al., “Epitaxial (Ba, Sr) TiO3 Capacitors with Extremely High Dielectric Constant for DRAM Applications,” IEDM 1997, Technical Digest, Dec. 1997, pages 257-260.
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