An Efficient Piezoelectric Energy Harvesting Interface Circuit

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An Efficient Piezoelectric Energy Harvesting Interface Circuit

Transcript Of An Efficient Piezoelectric Energy Harvesting Interface Circuit



An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier

Yimai Peng Inhee Lee

, Student Member, IEEE, Kyojin D. Choo , Member, IEEE, Sechang Oh , Member, IEEE, , Member, IEEE, Taekwang Jang, Student Member, IEEE, Yejoong Kim , Member, IEEE,
Jongyup Lim , Student Member, IEEE, David Blaauw , Fellow, IEEE, and Dennis Sylvester , Fellow, IEEE

Abstract— Piezoelectric energy harvesters (PEHs) are widely deployed in many self-sustaining systems, and proper rectifier circuits can significantly improve the energy conversion efficiency and, thus, increase the harvested energy. Various active rectifiers have been proposed in the past decade, such as synchronized switch harvesting on inductor (SSHI) and synchronous electric charge extraction (SECE). This article presents a sense-andset (SaS) rectifier that achieves maximum-power-point-tracking (MPPT) of PEHs and maintains optimal energy extraction for different input excitation levels and output voltages. The proposed circuit is fabricated in the 0.18-µm CMOS process with a 0.47-mm2 core area, a 230-nW active power, and a 7-nW leakage power. Measured with a commercial PEH device (Mide PPA-1022) at 85- and 60-Hz vibration frequency, the proposed circuit shows 512% and 541% power extraction improvement [figure of merit (FoM)] compared with an ideal full-bridge rectifier (FBR) for ON-resonance and OFF-resonance vibrations, respectively, while maintaining high efficiency across different input levels and PEH parameters.
Index Terms— DC–DC converter, maximum-power-pointtracking (MPPT), piezoelectric energy harvesting (PEH), rectifier.
E NERGY harvesting from ambient sources has drawn much interest in recent decades as it can provide power for energy-autonomous systems or significantly extend the lifetime for battery-powered systems. Among various energy harvesting techniques, the use of piezoelectric materials to harvest energy from mechanical vibration has become popular due to its high power density and good sustainability. A piezoelectric energy harvester (PEH) converts mechanical strain into electrical charge by means of the direct piezoelectric effect [1], and the charge can be extracted to generate ac power (usually in the nW–mW range), which can be applied to the electrical load. The output power of a given PEH can be
Manuscript received May 3, 2019; revised July 16, 2019 and August 27, 2019; accepted September 20, 2019. Date of publication October 15, 2019; date of current version November 22, 2019. This article was approved by Guest Editor Bernhard Wicht. (Corresponding author: Yimai Peng.)
Y. Peng, K. D. Choo, S. Oh, I. Lee, Y. Kim, J. Lim, D. Blaauw, and D. Sylvester are with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA (e-mail: [email protected]).
T. Jang is with the Department of Information Technology and Electrical Engineering, ETH Zürich, 8092 Zürich, Switzerland.
Color versions of one or more of the figures in this article are available online at
Digital Object Identifier 10.1109/JSSC.2019.2945262

optimized in terms of these two processes. On the one hand, the efficiency of the electromechanical energy conversion is optimized when the PEH is precisely vibrated at its resonant frequency, matching the natural characteristics of its massspring-damping system. This is rarely achieved in practical applications since most ambient vibration sources have a relatively unstable, broadband frequency spectrum [2]. Hence, some prior works have aimed to improve the bandwidth energy conversion, although with limited success [3], [4]. On the other hand, the design of interface circuits that perform impedance matching or maximum-power-point-tracking (MPPT) can significantly improve the charge extraction efficiency and, thus, increase the output power of the PEH. Most of the circuit techniques discussed in this article aim to improve the efficiency of this process rather than control the electromechanical conversion.
Among various interface circuits, full-bridge rectifiers (FBRs) are the most commonly used for their simplicity and stability [5], [6]. However, their power efficiencies are usually low since most of the PEH-generated charges are not extracted but remain within the large intrinsic capacitors of the PEHs. Several different techniques have been proposed to help with energy extraction from PEHs. The bias-flip (BF) technique, proposed by Ramadass et al. [7], manually sets a high bias voltage at the PEH’s output in order to extract more energy from a certain charge generated by the PEH. When the charge generation (current) changes the direction with the input vibration oscillation, the bias voltage is flipped. This is performed adiabatically to limit the energy loss of the operation. Prior BF-based works generally achieved the highest power efficiency when compared to other energy extraction techniques, and they can be divided into two categories, synchronized switch harvesting on inductor (SSHI) [8]–[10] and synchronized switch harvesting on capacitor (SSHC) [11]–[13], depending on whether an inductor or a capacitor array is used for the voltage flip. Other charge extraction techniques, such as synchronous electric charge extraction (SECE) [14] and energy pile-up resonant circuit [15], are generally less power efficient than the BF-based circuits but offer other advantages such as being more suitable for non-periodic vibrations.
However, all the above techniques have disadvantages for MPPT while extracting energy from PEHs. Theoretically, SSHI and SSHC can achieve near-MPPT in energy harvesting,

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Fig. 1. Modeling of the piezoelectric transducer. (a) Complete model with the electromechanical coupling. (b) Simplified model on the resonant frequency.

but they usually do not adapt to various input-vibration types (periodic or shock) and amplitudes, which decreases their power efficiencies in practical applications. SECE automatically adapts to different vibration amplitudes, but its efficiency is significantly degraded by the large intrinsic capacitor CP , and it generates unregulated output voltage for non-periodic vibrations.
In this article, we present a sense-and-set (SaS) interface circuit for PEHs, which is fundamentally different from prior techniques and achieves MPPT for arbitrary input vibrations. The proposed SaS technique has the following advantages over prior art.
1) SaS dynamically senses the PEH’s charge generation and sets the harvesting voltage accordingly. The power efficiency of SaS is, thus, adjusted to approach the theoretical limit.
2) SaS maintains MPPT for different vibration types, strengths/amplitudes, and PEH characteristic parameters without the need to manually tune the circuit for each condition.
3) SaS produces rectified output voltage without an additional passive rectifier, which eliminates the conduct loss (voltage drop) associated with the rectifier diode and improves the efficiency, especially for low-amplitude vibration (low-voltage) applications.
4) SaS de-couples the output node from the input so that a fixed output voltage does not interfere with the MPPT. In previous techniques, VOUT needs to change with the vibration strength to achieve high-power efficiency which clearly cannot be performed dynamically.
The remainder of this article is organized as follows. Section II presents the background of the PEH model and interface circuit approaches. The operation principle and implementation of the proposed SaS circuit are described in Sections III and IV, respectively. Section V shows the measurement results and analysis, while the conclusion is drawn in Section VI.
A. Modeling of Piezoelectric Transducers
The PEH or piezoelectric transducer generates electrical charges when the piezoelectric material is compressed or deflected by mechanical stress derived from external vibrations. It can be modeled as an electromechanical system, as shown in Fig. 1(a). The left part of the model illustrates

the mechanical structure of the PEH, in which RM , L M , and CM are the equivalent circuit components for the massspring-damping system of the piezoelectric layer. With the electromechanical coupling factor , power generated at the mechanical side is transformed to the electrical side and stored in the PEH intrinsic capacitor CP . When the PEH is excited at or close to its resonant frequency, L M and CM are cancelled out, and the model can be simplified into a model without the transformer, as shown in Fig. 1(b), where




RP = R2M .


IP defines the charges generated by the PEH in a certain time, and RP is the equivalent loss in the electromechanical conversion. According to the theory of the maximum power transfer, the load receives the maximum power

Pmax = 14 IP2 RP (3)

from the current source when

VP = VMPP = 1 IP RP . (4) 2

However, the impedance of CP is usually much smaller than

RP at the vibration frequency f (or ω). As a result, the VP

amplitude is much smaller than VMPP even for the open-circuit


VP-OC = IP (RP ||XC P ) = IP .


ωC P

Since 1/ωCP R P , VP-OC VMPP. For the same IP generated by the vibration, the low VP value limits the power

efficiency. Furthermore, VP will be affected by the impedance-

match condition between the PEH and interface circuits. The

ideal interface circuit that delivers Pmax to the load should

achieve complete impedance matching to the PEH, where the

load impedance X L = RL + ωL L is given by

RL = RP , ωL L = 1 . (6) ωC P
However, the required L L value is usually hundreds of Henries, which is impractical for system-on-chip (SoC) or even on-board systems. Thus, prior interface circuit designs tend to achieve better impedance match by placing VP to be near VMPP, which counteracts the negative effect of CP . The following paragraphs will continue this discussion in more detail.

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Fig. 2. Schematic and waveform for PEH through (a) FBR and (b) SSHI rectifier.

B. Full-Bridge Rectifier

The FBR is the most widely used interface circuit that allows energy harvesting from PEHs. As shown in Fig. 2(a), the PEH current IP first charges CP until VP reaches VOUT. Then, all of IP will flow through the FBR diodes to the load (represented by the green region) except for the loss by RP . When IP changes the direction with the input vibration, it must first discharge CP to 0 and then repeat the voltage build-up process in the other direction. During the charge–discharge operation, no power is transferred through the rectifier.
In FBR circuits, the output voltage VOUT must be between 0 and VP-OC in order to harvest energy from the PEH. Assuming ideal diodes (with no voltage drop) are used, the FBR delivers the maximum output power when VOUT is equal to half of VP-OC, according to [7]


= f C V 2 = IP2 .



P P-OC 2π ωC P

Comparing this to the theoretical maximum power, we get

Pmax-FBR = 2 1 = 2



π ωC P RP π QPEH

where QPEH is the quality factor of the piezoelectric transducer. Since generally 1/ωCP RP , then QPEH 1 (in the range of 10–100 for most of PEHs), and the maximum output power delivered by an FBR is significantly lower than
the theoretical maximum value.

C. Bias-Flip Rectifiers
One reason for the low-power efficiency of the FBR is that VP is limited within VP-OC, which is far below VMPP, which is shown as the blue line in Fig. 2(a). For the same PEH current IP , this much lower voltage results in the output power degradation. One effective way to improve the efficiency is to manually set a bias voltage (usually higher than VP-OC) on VP so that the same IP produces larger output power. When IP changes the direction, the bias voltage is then flipped so that no

energy is lost due to discharging CP . The circuits that utilize such a “BF” operation can be divided into two categories, SSHI [7]–[10] and SSHC [11]–[13], depending on whether they use an inductor or a capacitor array for the voltage flip.
Fig. 2(b) shows the schematic and waveform of an SSHI circuit. It still has an FBR for rectifying the output, but it has an additional switch-controlled inductor in parallel. VP is set manually to be a fixed high voltage, as demonstrated by the red line. IP will flow through the FBR to the load without charging CP , as indicated by the green region. When IP changes the direction, discharging CP is avoided by turning on the switch and shorting the PEH through the inductor LSW. By precisely controlling the switch’s turn-on period, SSHI, VP will be adiabatically flipped to a slightly lower negative value due to the circuit loss during the flip. Then, the inversed current IP charges VP back to VOUT, and energy harvesting begins again at this voltage.
From previous discussions, we know that for each interface circuit, the energy extraction from the PEH peaks when VP gets closer to VMPP. In the SSHI circuit, that is, when VP = VOUT = QBF VP-OC, and the maximum power delivered by an SSHI rectifier is


= 2fC V2




2 P





P P-OC BF π ωC P

where QBF is the combination of quality factors of the PEH and the CP LSW resonant circuit, and thus, usually 1 QBF < QPEH. Again, we compare it to the theoretical maximum power

Pmax-SSHI = 4Q F 1 = 4Q F .



π ωC P RP π QPEH

Although the power efficiency seems to be much better than that of an FBR, SSHI circuits does not achieve MPPT because the square-wave-shaped VP does not track the waveform of VMPP, which is defined by the vibration pattern (normally it will be a sine wave). In addition to the voltage-flip loss, which is shown by the gray dashed region in Fig. 2(b), it also

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Fig. 3. (a) SaS core circuit where C P = C P and CT = CT . (b) Set initial voltage VP on C P , C P , and CT . (c) Leave the PEH in the open circuit and let IP only charge C P . (d) Short C P and C P through an inductor until their voltages merge. (e) Transfer the energy in the inductor into the smaller capacitor. (f) Short CT and CT to get VMPP. (g) Waveforms showing the voltages for important nodes.

has a “dead time” when VP is larger than 2VMPP and all the current will flow through RP instead of the FBR (gray solid region). More importantly, in order to achieve the peak output power, SSHI circuits must set the value of VOUT wisely since it defines the amplitude of VP , which further determines the output power. In practical applications, it is hard to predict VP-OC and set the correct VOUT before the vibration happens. Also, the system output must be stable, not changing with the vibration’s amplitude, and an additional voltage converter will be needed, which further decreases the total power efficiency.
These limitations were partly addressed by some recent energy extraction techniques, such as SECE [14], which builds VP by the input current IP and harvests only at the peak value. However, these techniques lack the advantages of using a higher voltage at VP , so the overall power efficiency is less than the BF-based technique.
To achieve MPPT for PEHs, VP needs to be equal to VMPP, whose waveform and amplitude vary with the vibration.

Hence, there are two main challenges to dynamically adapt VP to VMPP.
1) Determining the Value of VMPP: It is not possible to directly observe VMPP due to the large intrinsic CP . Neither can we measure RP in the circuit (and multiply it by IP to get VMPP) since it is not in the real electrical domain but derived from the electromechanical model.
2) Maintaining VP Equal to VMPP: If we determine VMPP and VP is adapted to the VMPP level, its value will change with the oscillation. Since CP is large, keeping VP at/near VMPP requires a large energy transfer to charge or discharge CP , which results in the significant power loss. Our proposed SaS technique addresses these two challenges by adiabatically estimating the value of VMPP (the “sense” operation) and then adiabatically adjusting VP to it (the “set” operation). The operation of SaS will be introduced in the following paragraphs.

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A. Sense Phase
As previously discussed in Section II-A, a PEH’s opencircuit voltage VP-OC is far less than VMPP. The difference comes from the current that flows through CP , and, hence, we can recover VMPP by taking this current into account. Assuming the PEH is left in the open-circuit state, then

IP = IR + IC


where IR and IC are the current flowing through RP and CP , respectively. IR can be derived by VP /RP , in which RP is an unknown but fixed value for a given PEH. To measure IC , we can wait for a short-time period t and measure the voltage
accumulation V on a capacitor CP . IC is approximately constant during t, and its value is given by

IP = VP + CP V .




Then, VMPP can be recovered by

VMPP = 1 I RP = 1 VP + RP C P V .





Since RP , CP , and t are constant, we can “sense” VMPP no matter what the current VP is by measuring V .
However, since we want to keep t relatively short (for the approximation that IC is constant), the resulting V is usually in the sub-mV range. In order to operate with such a small signal, it is necessary to design delicate amplification and offset-cancelling circuits, which induce large power overhead. Fortunately, the energy difference from V on the capacitor CP is not small due to the large value of CP . In SaS, we use an inductor-based amplification where we transfer the energy difference into a smaller capacitor to generate higher voltage (tens of mV). Then, a serial-to-parallel switched capacitor array is used to further convert it to higher voltage (hundreds of mV).
Fig. 3(a) shows the SaS circuit schematic, which consists of multiple switches, capacitors, and a shared inductor. It can be reconfigured to different sub-circuits during the sense phase, as shown in Fig. 3(b)–(f); the red curve shows the direction of current flow. Initially, CP , CP , and CT are at the same potential as they are all connected and charged by the PEH [Fig. 3(b)]. When the sense phase begins, the PEH is left in the open-circuit mode for the time t, and a voltage difference
V develops between CP and CP [Fig. 3(c)]. Since CP and CP have relatively large capacitances, their energy difference is large, and we can use this for the charge-based amplification. In Fig. 3(d), we first short CP and CP through the inductor L to equalize their voltages, energizing L by

EL = 12 CP VP2 + CP (VP + V )2 − 2CP VP + 2V 2

= 1CP V 2.



EL is then transferred into a much smaller capacitor CT in

Fig. 3(e) to get a higher voltage VT

VT = 2EL = CP V .



2C T

Fig. 4. SaS rectifier in the set phase. (a) Down-convert operation. (b) Upconvert operation. (c) SaS waveform (without voltage flip) and its zoomed-in view region. (d) SaS waveform with voltage flip. (e) SaS efficiency with different MPPT ratios.

By replacing the V term in (13) with VT , we rewrite the

VMPP expression as follows:

VMPP = 12 IP RP = 21 ⎝VP + VT 2CT Ct P R2P ⎠. (16)

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If the constant






2 P


t is tuned to be 1, then VMPP

is the average of VP and VT . Thus, in Fig. 3(f), we short CT

and CT to generate VMPP and we can set VP to this value for

the MPPT operation.

B. Set Phase

The SaS circuit “sets” VP to VMPP after obtaining its value during the sense phase. This is performed by configuring the SaS circuit into an inductor-based up-down converter, as shown in Fig. 4(a) and (b). Converting the voltage up and down are adiabatic processes; the blue path shows the charging or discharging current that energizes L, and the green path shows the energy recycle back to the battery.
After converting VP to VMPP, the SaS maintains VP around this value by disconnecting itself from the PEH, as shown in Fig. 4(c). Then, IP gradually charges CP , causing VP to rise, and when VP exceeds the preset threshold, SaS harvests from CP by down-converting its voltage back to VMPP to maintain MPPT. The harvested energy is then transferred to the load (battery), and VOUT can be arbitrarily set regardless of the input amplitude.
The set phase lasts until VMPP drifts away after a time period, and the SaS ceases energy harvesting and enters the sense phase again. The new sense phase happens at the old VMPP value, and error correction is performed to get the new VMPP. Then, SaS converts VP to the new VMPP and begins another round of harvesting. By re-sensing repeatedly at a higher frequency than the vibration, the SaS technique achieves energy harvesting that tracks VMPP dynamically, as shown in Fig. 4(c). Also, when the current crosses zero and changes its direction, there is a voltage flipping operation so that VP remains positive, as will be further explained in Section III-C.
Since SaS always performs energy harvesting near the maximum power point, its power efficiency can approach 100% except for the loss caused by circuit non-ideality, which is given by




In (17), ηMPPT is the MPPT tracking error for VP not perfectly following VMPP, and ηMPPT characterizes the dead-time loss since SaS does not harvest energy during the sense phase. There is a tradeoff between ηMPPT and ηDT when choosing the SaS frequency. More frequent SaS operations increase the VMPP tracking precision and, thus, improve ηMPPT, but degrade ηDT because the circuit spends more time overall in determining VMPP.
With the optimal frequency, the efficiency of ηMPPTηDT is usually around 85% or higher. However, the voltage conver-
sion loss due to the switching and conduction activities usually
dominates the total efficiency number. Although the inductor-
based voltage converter has a high efficiency itself, it transfers the energy in CP (∝ CP VP2) which is several times larger than the energy generated by the PEH in each cycle (∝ VP2/RP ). Hence, the energy loss in the voltage conversion is amplified by this ratio, resulting in a low ηVC.

Fig. 4(e) shows the post-pex simulation result for (17). The x -axis is the proportion of VP /VMPP and the y-axis is the overall efficiency of the system. We know from Section II-A that the efficiency should be optimized when VP /VMPP = 1 in the ideal condition. However, larger VP /VMPP ratio results in larger amount of energy transfer, which significantly reduce ηVC as well as the overall efficiency. Hence, the system efficiency peaks at smaller VP /VMPP which means we track VMPP at a proportion of its exact value. In such cases, the overall efficiency is around 42%, mainly due to the low conversion efficiency. To further increase the overall efficiency, we could probably use low-series-resistance (LSR) inductor or other converter topologies to reduce the conversion loss.

C. Flipping Phase
The advantages of SaS come from its dynamic adjustment of VP according to the vibration waveform. However, this restricts the use of conventional rectifiers that handle negative voltages. To address this problem, we implemented a flipping phase which is a special case of the set phase. When the VMPP generated in the sense phase is negative, it indicates that IP has changed direction and VMPP entered its negative half-cycle. VP is then converted to this negative VMPP as usual in the set phase but followed by a flipping operation, where the connections to the two PEH terminals are swapped. As a result, VP is flipped to the positive value and future VMPP will stay positive until the next flipping happens.
The flipping phase happens twice for each vibration cycle, and it ensures that VP remains positive without the use of rectifiers, as shown in Fig. 4(d). Some energy loss may be incurred in the flipping operation; however, since the VP values at the time of flipping is near zero, the loss is typically negligible.

D. Calibration Phase

As previously mentioned in (16), it is necessary to tune

the constant






2 P



to be 1 so that VMPP


be obtained by averaging VP and VT . Unlike CP and CT ,

the value of RP is difficult to measure or control, and it varies

among different PEHs. Moreover, there may be mismatches

on VT due to circuit non-idealities, resulting in inaccurate

VMPP estimates. To compensate for this, the SaS circuit

performs self-calibration by adjusting the sense phase time t

automatically without knowing the values of these parameters.

The calibration process is very similar to the sense phase

in terms of obtaining VMPP. But instead of entering the set

phase, SaS converts VP to 2VMPP and performs another sense

operation at this voltage. If the voltage VT appears to be

negative (which means VP was over-estimated in the previous

sense phase due to a VT constant larger than 1), SaS decreases

t to get a lower VT and compensate for the larger constant.

The process is repeated, and t is adjusted in a digit-step

manner until there is a positive VT , which indicates over-


The calibration phase only needs to be performed once when

SaS is connected to a new PEH. Once the right t value is

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Fig. 5. Top-level diagram for the proposed SaS circuit (grayed area indicates components that are off-chip).


power path between the PEH and the load, the transistor sizes are selected to optimize the total conduction loss and switching loss during voltage conversion. A list of detailed switch sizes and other parameters can be found in Table I.

tuned, the SaS circuit can harvest energy from the PEH with MPPT for arbitrary vibration inputs.
A. Inductor-Sharing Circuit
The top-level schematic of the proposed SaS circuit is shown in Fig. 5. The lower part is the inductor-sharing circuit, which performs the adiabatic SaS operations. In addition to what was described in Section II-A, there is one additional switch pair that connects PEH with the SaS input to assist the flipping phase. By combining the “flip” switch with the up-down converter that was previously introduced, SaS eliminates the passive rectifier which limits the efficiency for low vibration (voltage) applications.
All switches are implemented with CMOS transmission gates but with different sizing considerations. For switches with only a control purpose, minimum-sized transistors are used for low switching loss. For the switches on the

B. Clock Generator
SaS clocks are implemented on-chip and divided into three domains.
1) The MPPT clock ( fMPPT) defines the frequency of SaS refreshing its VMPP value by performing SaS operations. This clock frequency, which is denoted by fMPPT, is usually in the 1-kHz range, tens of times higher than the vibration frequency.
2) The digital counter clock ( fCNT) is related to the sense phase time t. Since t = NCNT/ fCNT, a larger fCNT means finer control over t but higher power overhead. Hence, the clock frequency is chosen to be 100 kHz.
3) The comparator clock ( fCOMP) runs the clockedcomparator and controls the switches for voltage conversion and is implemented to be 10 MHz in order to achieve high power efficiency by decreasing timing errors.
For low-power operation, the three clocks are generated with the five-stage ring oscillators (ROs) proposed by Lee et al. [16] to achieve constant energy-per-cycle across wide frequency range. As shown in Fig. 6(a), the ROs consist of leakagebased inverters with an additional low-Vth (LVT) device pair in the middle. When the input voltage flips, the leakage path through the LVT latch controls the delay of output toggling and determines the oscillation frequency. Further tuning on the frequency can be achieved by adding a current path with the parallel transistors. The voltage to bias parallel transistors (VBP or VBN) are generated by diode-connected transistors and selected with a 64-to-1 multiplexer.

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Fig. 7. Micrograph of the test chip fabricated in the 180-nm CMOS process. The active area of the circuit is 0.47 mm2. (1) Bias voltage generator.
(2) ROs. (3) Scan chain for tuning. (4) Clocked comparators. (5) Pulse
generator. (6) Inductor sharing circuit.

Fig. 6. (a) Circuit schematic of the five-stage RO and its biasing circuit. (b) fCNT and fCMOP that run at higher frequency are awoken by fMPPT at a specific time. (c) Schematic of two-stage comparator.
Among the three clocks, fMPPT needs to be always-on in order to track VMPP in real time. It will result in large power overhead if we run the oscillator at 10 MHz and divide it to generate fMPPT. Instead, we implemented three separate ROs in SaS, and the fast ROs ( fCNT and fCOMP) are only awoken when their controlled blocks are used. Fig. 6(b) shows the duty-cycled clocks for the counter and comparators.
C. Pulse Generation and Clock Counter
The sequential SaS operation is hard-coded in the SaS, and its order is determined by the pulse generation circuit. The circuit takes fMPPT as input, propagating its rising edge through multiple delay stages, and generates pulses that activate different switches in SaS. The delay cells are similar to what is used in clock generation, with specific bias voltage to control its delay and the pulse width.

Fig. 8. Breakdown of power consumptions of SaS sub-circuit blocks under the normal operation. The total power (230 nW) is measured in a room temperature and the proportion numbers come from post-pex simulation.
Especially, the pulse width that defines t cannot be hardcoded as it needs to be adjustable during the calibration phase. Thus, we implemented a digital counter that counts fCNT until it reaches a given number N. Then
t = N (18) fCNT
where fCNT determines the resolution of t, and N gives the range. The value of N is stored in another counter-like structure that is kept tuned during the calibration phase.
D. Comparators The SaS circuit performs voltage conversion when it
changes VP . The voltage conversion efficiency ηVC, which dominates the overall SaS efficiency as we discussed,

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Fig. 9. Measured transient waveform of VP , VOUT, and the VFlip (flip control signal) under different vibrations in the long term (top) and its zoom-in view regions (bottom). Amplitude/frequency for strong and weak periodical vibrations are 2 g/85 Hz and 0.2 g/85 Hz, respectively. The shock vibration has an
amplitude of 3 g, with a (rough) period of 1 s.

is affected by the timing error of the switches. To determine the correct timing signals for the switches, we implemented two comparators in SaS, as shown in Fig. 6(c). The first one compares VP with the target voltage and produces turn-off signals when VP has been converted to the target voltage. The second one performs cross-zero detection for the inductor L’s current by measuring its terminal voltage and helps with the energy recycling from L.
In order to control the switching activities for voltage conversion while maintaining high efficiency, the comparator clock signal fCOMP needs to be approximately 10 MHz to reduce timing error. We implemented fCOMP in a highly dutycycled manner where only when a switching activity begins, the fastest oscillator is enabled and provides clocks to the comparator. Since the switching time is only a small portion of the total SaS time, both the comparator and the corresponding oscillator will be idle for most of the time. By this technique, we reduced the power consumption of timing control from 14.5 μW to 151 nW, as shown in Section V.
E. Switch Controller and Switch Drivers
The sequential signals generated by the pulse generator, clock counter, and comparators need to be mapped into the final control signals that apply to S1–S9. Thus, a look-up table is implemented, and the switch control signals are buffered to drive some of the large switches in SaS. The power supply for the switch controller as well as other circuit blocks comes from VOUT, which is the harvested energy. But for testing

purpose, we use separate 2-V supply so that we can quantify the power consumption by the SaS circuit. To extend the output voltage and the operation range of SaS, the switches can be implemented with high-voltage transistors, and a level converter may be inserted between it and the controller circuit.
The proposed SaS circuit [17] is designed and fabricated in the 180-nm CMOS process with a core area of 0.47 mm2, as shown in Fig. 7. The measured leakage and active power in the room temperature for SaS are 7 and 230 nW, respectively, and Fig. 8 shows the power proportion of each circuit block when SaS is in operation. In addition, 91% of the clock generation power and 88% of the comparator power are related to the high-frequency operations ( fCOMP), while the latter only takes about 1% of the total operation time. The fabricated chip was tested with a commercially available piezoelectrical transducer, PPA-1022 from Mide Technology, Woburn, MA, USA. The transducer was clamped on the PPA9001 kit (position 0 with 11.2-g tip mass) and mounted on a shaker table (Sentek Dynamic IA20N) as the vibration source. The transducer is excited with a 85-Hz sinusoidal signal (OFFresonance), a 53-Hz sinusoidal signal (ON-resonance), as well as pulse/chock signals.
Fig. 9 shows the SaS start-up and harvesting waveforms with 85-Hz periodic and shock vibrations. Given an initial vibration to the PEH, the SaS circuit harvests energy from it and gradually builds up VOUT and VP amplitude until they

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Fig. 10. Measured output power of SaS and ideal FBR for (a) different VOUT values with 0.03 g/53 Hz vibration, (b) different VOUT values with 0.09 g/53 Hz vibration, (c) different vibration strengths with Vlimit = 2 V, (d) different vibration strengths with Vlimit = 2.4 V, (e) different VOUT values with 0.5 g/85 Hz vibration, and (f) different fMPPT values and different input vibration strengths.

reach 2 V, the voltage limit for this CMOS process. Since the VMPP value for the strong vibration may exceed 2 V, VP stops tracking it but maintaining at 2 V to approach VMPP, and SaS performs partial MPPT for energy harvesting (left bottom in Fig. 9). This limitation can be removed by implementing the inductor sharing circuit in high-voltage process so that higher VOUT can be expected. When the input vibration is relatively weak (right bottom in Fig. 9), VP tracks VMPP for its whole period, and optimized energy extraction from the PEH is achieved. If the vibration is of pulse type, which is

common in practical applications, VP still tracks the input and performs MPPT for the activation period and remains static for the intermittent time. In addition, VOUT is kept at the same value with different vibration strengths and types, which decouples the output node from the input and makes SaS self-adaptable to various vibration sources.
We measured the electrical output power of the PEH using an SaS circuit and compared it with that obtained using an ideal FBR, which we implemented off-chip with active diodes (MAX40200 with <10-mV voltage drop). Fig. 10(a) and (b)

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